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minsoc
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https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2F&
Fri, 29 Mar 2024 15:59:37 +0100
FeedCreator 1.7.2
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or1200.h includes a CLABLE macro which uses __USER_LABEL_PREFIX__(from compiler defined ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=74
<div><strong>Rev 74 - rfajardo</strong> (4 file(s) modified)</div><div>or1200.h includes a CLABLE macro which uses __USER_LABEL_PREFIX__(from compiler defined ...</div>~ /minsoc/trunk/sw/support/common.mk<br />~ /minsoc/trunk/sw/support/except.S<br />~ /minsoc/trunk/sw/support/or1200.h<br />~ /minsoc/trunk/sw/support/reset.S<br />
rfajardo
Tue, 10 May 2011 19:06:26 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=74
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Makefile does not automatic clean anymore. In Windows rm -f ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=73
<div><strong>Rev 73 - rfajardo</strong> (5 file(s) modified)</div><div>Makefile does not automatic clean anymore. In Windows rm -f ...</div>~ /minsoc/trunk/sim/modelsim/compile_design.bat<br />~ /minsoc/trunk/sim/modelsim/prepare_modelsim.bat<br />~ /minsoc/trunk/sim/modelsim/run_sim.bat<br />+ /minsoc/trunk/syn/setup.bat<br />~ /minsoc/trunk/syn/src/Makefile<br />
rfajardo
Tue, 10 May 2011 13:52:00 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=73
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Adding Windows batch files to run a Modelsim simulation.
...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=72
<div><strong>Rev 72 - rfajardo</strong> (3 file(s) modified)</div><div>Adding Windows batch files to run a Modelsim simulation. <br />
...</div>+ /minsoc/trunk/sim/modelsim/compile_design.bat<br />+ /minsoc/trunk/sim/modelsim/prepare_modelsim.bat<br />+ /minsoc/trunk/sim/modelsim/run_sim.bat<br />
rfajardo
Tue, 10 May 2011 12:50:07 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=72
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Modelsim whines about missing timescales:
-minsoc_bench.v, minsoc_memory_model.v and ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=71
<div><strong>Rev 71 - rfajardo</strong> (3 file(s) modified)</div><div>Modelsim whines about missing timescales: <br />
-minsoc_bench.v, minsoc_memory_model.v and ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_memory_model.v<br />~ /minsoc/trunk/bench/verilog/vpi/dbg_comm_vpi.v<br />
rfajardo
Tue, 10 May 2011 10:34:10 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=71
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Including a global timescale under minsoc/rtl/verilog to control simulation. It ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=70
<div><strong>Rev 70 - rfajardo</strong> (10 file(s) modified)</div><div>Including a global timescale under minsoc/rtl/verilog to control simulation. It ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/std/minsoc_bench_defines.v<br />+ /minsoc/trunk/rtl/verilog/timescale.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />+ /minsoc/trunk/sim/modelsim<br />+ /minsoc/trunk/sim/modelsim/compile_design.sh<br />+ /minsoc/trunk/sim/modelsim/prepare_modelsim.sh<br />+ /minsoc/trunk/sim/modelsim/run_sim.sh<br />
rfajardo
Tue, 10 May 2011 10:06:07 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=70
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backend update:
-minsoc_bench_defines.v
...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=69
<div><strong>Rev 69 - rfajardo</strong> (21 file(s) modified)</div><div>backend update: <br />
-minsoc_bench_defines.v<br />
...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/gcc-opt.mk<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/gcc-opt.mk<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/board.h<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/gcc-opt.mk<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/or1200_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/orp.ld<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/spartan3e_starter_kit_eth.ucf<br />~ /minsoc/trunk/backend/std/configure<br />+ /minsoc/trunk/backend/std/gcc-opt.mk<br />+ /minsoc/trunk/backend/std/minsoc_bench_defines.v<br />- /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />~ /minsoc/trunk/sw/support/Makefile.inc<br />
rfajardo
Thu, 05 May 2011 18:11:35 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=69
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Still one configuration mismatch on minsoc_defines.v:
-MEMORY_ADR_WIDTH ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=68
<div><strong>Rev 68 - rfajardo</strong> (1 file(s) modified)</div><div>Still one configuration mismatch on minsoc_defines.v:<br />
-MEMORY_ADR_WIDTH ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_defines.v<br />
rfajardo
Tue, 03 May 2011 14:25:40 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=68
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Constraint file for backend spartan3a_dsp_kit.ucf was configured to include the ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=67
<div><strong>Rev 67 - rfajardo</strong> (1 file(s) modified)</div><div>Constraint file for backend spartan3a_dsp_kit.ucf was configured to include the ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf<br />
rfajardo
Tue, 03 May 2011 14:17:59 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=67
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spartan3e_starter_kit requires special configuration of or1200_r3.
For that, configure script ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=66
<div><strong>Rev 66 - rfajardo</strong> (2 file(s) modified)</div><div>spartan3e_starter_kit requires special configuration of or1200_r3. <br />
<br />
For that, configure script ...</div>~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/or1200_defines.v<br />
rfajardo
Tue, 03 May 2011 13:42:39 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=66
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Files missing in the last commit.
backend/std/configure
sw: eth, uart and ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=65
<div><strong>Rev 65 - rfajardo</strong> (4 file(s) modified)</div><div>Files missing in the last commit. <br />
backend/std/configure<br />
sw: eth, uart and ...</div>+ /minsoc/trunk/backend/std/configure<br />+ /minsoc/trunk/sw/drivers/Makefile<br />+ /minsoc/trunk/sw/eth/Makefile<br />+ /minsoc/trunk/sw/uart/Makefile<br />
rfajardo
Tue, 03 May 2011 12:36:44 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=65
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firmware makefiles:
-every firmware makefile has now ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=64
<div><strong>Rev 64 - rfajardo</strong> (61 file(s) modified)</div><div>firmware makefiles:<br />
-every firmware makefile has now ...</div>+ /minsoc/trunk/backend/ml509<br />- /minsoc/trunk/backend/ml509.ucf<br />+ /minsoc/trunk/backend/ml509/ml509.ucf<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit<br />- /minsoc/trunk/backend/spartan3a_dsp_kit.ucf<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/board.h<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_defines.v<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/orp.ld<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf<br />+ /minsoc/trunk/backend/spartan3e_starter_kit<br />- /minsoc/trunk/backend/spartan3e_starter_kit.ucf<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/board.h<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/orp.ld<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf<br />+ /minsoc/trunk/backend/std<br />+ /minsoc/trunk/backend/std/board.h<br />+ /minsoc/trunk/backend/std/minsoc_defines.v<br />+ /minsoc/trunk/backend/std/orp.ld<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />- /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />~ /minsoc/trunk/sw/drivers/can.c<br />+ /minsoc/trunk/sw/drivers/common.mk<br />~ /minsoc/trunk/sw/drivers/eth.c<br />~ /minsoc/trunk/sw/drivers/i2c.c<br />- /minsoc/trunk/sw/drivers/Makefile<br />~ /minsoc/trunk/sw/drivers/uart.c<br />+ /minsoc/trunk/sw/eth/common.mk<br />~ /minsoc/trunk/sw/eth/eth.c<br />- /minsoc/trunk/sw/eth/Makefile<br />- /minsoc/trunk/sw/support/board.h<br />+ /minsoc/trunk/sw/support/common.mk<br />/minsoc/trunk/sw/support/Makefile<br />~ /minsoc/trunk/sw/support/Makefile.inc<br />- /minsoc/trunk/sw/support/orp.ld<br />~ /minsoc/trunk/sw/support/reset.S<br />~ /minsoc/trunk/sw/support/tick.c<br />+ /minsoc/trunk/sw/uart/common.mk<br />- /minsoc/trunk/sw/uart/Makefile<br />~ /minsoc/trunk/sw/uart/uart.c<br />- /minsoc/trunk/syn/blackboxes/OR1K_startup_generic.v<br />- /minsoc/trunk/syn/buildSupport/adbg_top.xst<br />- /minsoc/trunk/syn/buildSupport/eth_top.xst<br />- /minsoc/trunk/syn/buildSupport/minsoc_startup_top.prj<br />- /minsoc/trunk/syn/buildSupport/minsoc_startup_top.xst<br />~ /minsoc/trunk/syn/buildSupport/minsoc_top.prj<br />- /minsoc/trunk/syn/buildSupport/minsoc_top.xst<br />- /minsoc/trunk/syn/buildSupport/or1200_top.xst<br />- /minsoc/trunk/syn/buildSupport/uart_top.xst<br />- /minsoc/trunk/syn/Makefile<br />+ /minsoc/trunk/syn/src<br />+ /minsoc/trunk/syn/src/adbg_top.xst<br />+ /minsoc/trunk/syn/src/eth_top.xst<br />+ /minsoc/trunk/syn/src/Makefile<br />+ /minsoc/trunk/syn/src/minsoc_top.xst<br />+ /minsoc/trunk/syn/src/or1200_top.xst<br />+ /minsoc/trunk/syn/src/uart_top.xst<br />- /minsoc/trunk/utils/contributions/.directory<br />
rfajardo
Tue, 03 May 2011 11:01:33 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=64
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Adding a functional synthesis Makefile system. Still needs a reviews ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=63
<div><strong>Rev 63 - rfajardo</strong> (26 file(s) modified)</div><div>Adding a functional synthesis Makefile system. Still needs a reviews ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit.ucf<br />~ /minsoc/trunk/rtl/verilog/altera_pll.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />+ /minsoc/trunk/syn<br />+ /minsoc/trunk/syn/blackboxes<br />+ /minsoc/trunk/syn/blackboxes/adbg_top.v<br />+ /minsoc/trunk/syn/blackboxes/eth_top.v<br />+ /minsoc/trunk/syn/blackboxes/OR1K_startup_generic.v<br />+ /minsoc/trunk/syn/blackboxes/or1200_top.v<br />+ /minsoc/trunk/syn/blackboxes/uart_top.v<br />+ /minsoc/trunk/syn/buildSupport<br />+ /minsoc/trunk/syn/buildSupport/adbg_top.prj<br />+ /minsoc/trunk/syn/buildSupport/adbg_top.xst<br />+ /minsoc/trunk/syn/buildSupport/eth_top.prj<br />+ /minsoc/trunk/syn/buildSupport/eth_top.xst<br />+ /minsoc/trunk/syn/buildSupport/minsoc_startup_top.prj<br />+ /minsoc/trunk/syn/buildSupport/minsoc_startup_top.xst<br />+ /minsoc/trunk/syn/buildSupport/minsoc_top.prj<br />+ /minsoc/trunk/syn/buildSupport/minsoc_top.xst<br />+ /minsoc/trunk/syn/buildSupport/or1200_top.prj<br />+ /minsoc/trunk/syn/buildSupport/or1200_top.xst<br />+ /minsoc/trunk/syn/buildSupport/uart_top.prj<br />+ /minsoc/trunk/syn/buildSupport/uart_top.xst<br />+ /minsoc/trunk/syn/doc<br />+ /minsoc/trunk/syn/doc/guideTop.pdf<br />+ /minsoc/trunk/syn/Makefile<br />
rfajardo
Fri, 29 Apr 2011 17:26:11 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=63
-
Wrapping different family modules of same manufacturer in a single ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=62
<div><strong>Rev 62 - rfajardo</strong> (4 file(s) modified)</div><div>Wrapping different family modules of same manufacturer in a single ...</div>+ /minsoc/trunk/rtl/verilog/altera_pll.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v<br />- /minsoc/trunk/rtl/verilog/minsoc_pll.v<br />+ /minsoc/trunk/rtl/verilog/xilinx_dcm.v<br />
rfajardo
Fri, 29 Apr 2011 10:32:37 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=62
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Removing supposely defined external function, which don't exist anymore.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=61
<div><strong>Rev 61 - rfajardo</strong> (1 file(s) modified)</div><div>Removing supposely defined external function, which don't exist anymore.</div>~ /minsoc/trunk/sw/support/support.h<br />
rfajardo
Fri, 29 Apr 2011 09:45:17 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=61
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Selection of memory model or implementation memory is now made ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=60
<div><strong>Rev 60 - rfajardo</strong> (8 file(s) modified)</div><div>Selection of memory model or implementation memory is now made ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/bench/verilog/minsoc_memory_model.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />- /minsoc/trunk/sim/bin/minsoc_memory.txt<br />- /minsoc/trunk/sim/bin/minsoc_model.txt<br />+ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />~ /minsoc/trunk/sim/run/generate_bench<br />
rfajardo
Thu, 28 Apr 2011 22:44:09 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=60
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undefinition of NEGATIVE_RESET on minsoc_bench_defines.v cannot affect other inclusions of ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=59
<div><strong>Rev 59 - rfajardo</strong> (2 file(s) modified)</div><div>undefinition of NEGATIVE_RESET on minsoc_bench_defines.v cannot affect other inclusions of ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />
rfajardo
Thu, 28 Apr 2011 21:59:30 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=59
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Standard definitions depended on implementation order. Now, this should be ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=58
<div><strong>Rev 58 - rfajardo</strong> (2 file(s) modified)</div><div>Standard definitions depended on implementation order. Now, this should be ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />
rfajardo
Thu, 28 Apr 2011 21:50:11 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=58
-
If a FPGA manufacturer is selected, the FPGA families of ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=57
<div><strong>Rev 57 - rfajardo</strong> (1 file(s) modified)</div><div>If a FPGA manufacturer is selected, the FPGA families of ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />
rfajardo
Thu, 28 Apr 2011 21:27:09 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=57
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Macros for all Altera family devices and pll instantiation
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=56
<div><strong>Rev 56 - javieralso</strong> (4 file(s) modified)</div><div>Macros for all Altera family devices and pll instantiation</div>~ /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_pll.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />
javieralso
Thu, 21 Apr 2011 22:40:38 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=56
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Adjusting Makefiles to compile correctly with new firmware updates.
1) ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=55
<div><strong>Rev 55 - rfajardo</strong> (4 file(s) modified)</div><div>Adjusting Makefiles to compile correctly with new firmware updates. <br />
<br />
1) ...</div>~ /minsoc/trunk/sw/eth/Makefile<br />~ /minsoc/trunk/sw/support/int.c<br />~ /minsoc/trunk/sw/support/Makefile<br />~ /minsoc/trunk/sw/uart/Makefile<br />
rfajardo
Wed, 20 Apr 2011 14:12:19 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=55
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