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minsoc WebSVN RSS feed - minsoc https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2F& Mon, 19 Oct 2020 21:47:17 +0100 FeedCreator 1.7.2 Updating configure script messages. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=86 <div><strong>Rev 86 - rfajardo</strong> (3 file(s) modified)</div><div>Updating configure script messages.</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br /> rfajardo Tue, 06 Sep 2011 15:41:45 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=86 Central project definition under prj. Synthesis and simulation take their ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=85 <div><strong>Rev 85 - rfajardo</strong> (55 file(s) modified)</div><div>Central project definition under prj. Synthesis and simulation take their ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/trunk/backend/std/configure<br />+ /minsoc/trunk/prj<br />+ /minsoc/trunk/prj/altera<br />+ /minsoc/trunk/prj/Makefile<br />+ /minsoc/trunk/prj/scripts<br />+ /minsoc/trunk/prj/scripts/simprj.sh<br />+ /minsoc/trunk/prj/scripts/xilinxprj.sh<br />+ /minsoc/trunk/prj/scripts/xilinxxst.sh<br />+ /minsoc/trunk/prj/sim<br />+ /minsoc/trunk/prj/sim/adbg_top.src<br />+ /minsoc/trunk/prj/sim/ethmac.src<br />+ /minsoc/trunk/prj/sim/jtag_top.src<br />+ /minsoc/trunk/prj/sim/minsoc.src<br />+ /minsoc/trunk/prj/sim/minsoc_top.src<br />+ /minsoc/trunk/prj/sim/or1200_top.src<br />+ /minsoc/trunk/prj/sim/uart_top.src<br />+ /minsoc/trunk/prj/src<br />+ /minsoc/trunk/prj/src/adbg_top.prj<br />+ /minsoc/trunk/prj/src/blackboxes<br />+ /minsoc/trunk/prj/src/blackboxes/ethmac.v<br />- /minsoc/trunk/prj/src/blackboxes/eth_top.v<br />+ /minsoc/trunk/prj/src/ethmac.prj<br />+ /minsoc/trunk/prj/src/jtag_top.prj<br />+ /minsoc/trunk/prj/src/minsoc_top.prj<br />+ /minsoc/trunk/prj/src/or1200_top.prj<br />+ /minsoc/trunk/prj/src/uart_top.prj<br />+ /minsoc/trunk/prj/xilinx<br />+ /minsoc/trunk/prj/xilinx/adbg_top.prj<br />+ /minsoc/trunk/prj/xilinx/adbg_top.xst<br />+ /minsoc/trunk/prj/xilinx/ethmac.prj<br />+ /minsoc/trunk/prj/xilinx/ethmac.xst<br />+ /minsoc/trunk/prj/xilinx/jtag_top.prj<br />+ /minsoc/trunk/prj/xilinx/jtag_top.xst<br />+ /minsoc/trunk/prj/xilinx/minsoc_top.prj<br />+ /minsoc/trunk/prj/xilinx/minsoc_top.xst<br />+ /minsoc/trunk/prj/xilinx/or1200_top.prj<br />+ /minsoc/trunk/prj/xilinx/or1200_top.xst<br />+ /minsoc/trunk/prj/xilinx/uart_top.prj<br />+ /minsoc/trunk/prj/xilinx/uart_top.xst<br />- /minsoc/trunk/sim/bin<br />~ /minsoc/trunk/sim/modelsim/compile_design.bat<br />~ /minsoc/trunk/sim/modelsim/compile_design.sh<br />~ /minsoc/trunk/sim/run/generate_bench<br />- /minsoc/trunk/syn/blackboxes<br />- /minsoc/trunk/syn/buildSupport/adbg_top.prj<br />- /minsoc/trunk/syn/buildSupport/eth_top.prj<br />- /minsoc/trunk/syn/buildSupport/minsoc_top.prj<br />- /minsoc/trunk/syn/buildSupport/or1200_top.prj<br />- /minsoc/trunk/syn/buildSupport/uart_top.prj<br />- /minsoc/trunk/syn/src<br />+ /minsoc/trunk/syn/xilinx<br />+ /minsoc/trunk/syn/xilinx/Makefile<br /> rfajardo Tue, 06 Sep 2011 15:34:18 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=85 syn/blackboxes/eth_top.v: -module is now called ethmac instead ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=84 <div><strong>Rev 84 - rfajardo</strong> (1 file(s) modified)</div><div>syn/blackboxes/eth_top.v:<br /> -module is now called ethmac instead ...</div>~ /minsoc/trunk/syn/blackboxes/eth_top.v<br /> rfajardo Mon, 05 Sep 2011 14:58:07 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=84 minsoc-install.sh: bzip2 program was being used, but its existance on ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=83 <div><strong>Rev 83 - rfajardo</strong> (1 file(s) modified)</div><div>minsoc-install.sh: bzip2 program was being used, but its existance on ...</div>~ /minsoc/trunk/utils/setup/minsoc-install.sh<br /> rfajardo Thu, 25 Aug 2011 09:36:09 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=83 minsoc-install.sh: problems with copying the GNU Toolchain from download to ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=82 <div><strong>Rev 82 - rfajardo</strong> (2 file(s) modified)</div><div>minsoc-install.sh: problems with copying the GNU Toolchain from download to ...</div>+ /minsoc/trunk/utils/setup/install_time.txt<br />~ /minsoc/trunk/utils/setup/minsoc-install.sh<br /> rfajardo Mon, 22 Aug 2011 10:18:30 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=82 Installation script complete, nice text feedback, output logs and better ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=81 <div><strong>Rev 81 - rfajardo</strong> (3 file(s) modified)</div><div>Installation script complete, nice text feedback, output logs and better ...</div>~ /minsoc/trunk/utils/setup/beautify.sh<br />~ /minsoc/trunk/utils/setup/minsoc-install.sh<br />~ /minsoc/trunk/utils/setup/required-cygwin-tools.txt<br /> rfajardo Sun, 21 Aug 2011 23:14:37 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=81 Establishing a better Makefile system for firmwares. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=80 <div><strong>Rev 80 - rfajardo</strong> (21 file(s) modified)</div><div>Establishing a better Makefile system for firmwares.</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/gcc-opt.mk<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/gcc-opt.mk<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/gcc-opt.mk<br />~ /minsoc/trunk/backend/std/gcc-opt.mk<br />~ /minsoc/trunk/sw/drivers/can.c<br />- /minsoc/trunk/sw/drivers/common.mk<br />~ /minsoc/trunk/sw/drivers/eth.c<br />~ /minsoc/trunk/sw/drivers/i2c.c<br />~ /minsoc/trunk/sw/drivers/Makefile<br />~ /minsoc/trunk/sw/drivers/uart.c<br />- /minsoc/trunk/sw/eth/common.mk<br />~ /minsoc/trunk/sw/eth/eth.c<br />~ /minsoc/trunk/sw/eth/Makefile<br />- /minsoc/trunk/sw/support/common.mk<br />~ /minsoc/trunk/sw/support/Makefile<br />~ /minsoc/trunk/sw/support/Makefile.inc<br />~ /minsoc/trunk/sw/support/reset.S<br />~ /minsoc/trunk/sw/support/support.c<br />- /minsoc/trunk/sw/uart/common.mk<br />~ /minsoc/trunk/sw/uart/Makefile<br />~ /minsoc/trunk/sw/uart/uart.c<br /> rfajardo Fri, 19 Aug 2011 11:05:49 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=80 minsoc-install.sh: rpath corrected. required-cygwin-tools: updated https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=79 <div><strong>Rev 79 - rfajardo</strong> (2 file(s) modified)</div><div>minsoc-install.sh: rpath corrected.<br /> required-cygwin-tools: updated</div>~ /minsoc/trunk/utils/setup/minsoc-install.sh<br />~ /minsoc/trunk/utils/setup/required-cygwin-tools.txt<br /> rfajardo Thu, 18 Aug 2011 18:14:42 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=79 minsoc-install.sh: Advanced JTAG bridge compilation needs to know where the ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=78 <div><strong>Rev 78 - rfajardo</strong> (1 file(s) modified)</div><div>minsoc-install.sh: Advanced JTAG bridge compilation needs to know where the ...</div>~ /minsoc/trunk/utils/setup/minsoc-install.sh<br /> rfajardo Thu, 18 Aug 2011 18:04:36 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=78 New tool requirements for installing Icarus Verilog. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=77 <div><strong>Rev 77 - rfajardo</strong> (1 file(s) modified)</div><div>New tool requirements for installing Icarus Verilog.</div>~ /minsoc/trunk/utils/setup/minsoc-install.sh<br /> rfajardo Thu, 18 Aug 2011 17:46:15 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=77 Including a script allowing the installation of MinSoC and all ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=76 <div><strong>Rev 76 - rfajardo</strong> (4 file(s) modified)</div><div>Including a script allowing the installation of MinSoC and all ...</div>+ /minsoc/trunk/utils/setup<br />+ /minsoc/trunk/utils/setup/beautify.sh<br />+ /minsoc/trunk/utils/setup/minsoc-install.sh<br />+ /minsoc/trunk/utils/setup/required-cygwin-tools.txt<br /> rfajardo Thu, 18 Aug 2011 17:37:11 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=76 Adapting minsoc_top.v and minsoc_verilog_files.txt to new names for top modules ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=75 <div><strong>Rev 75 - rfajardo</strong> (2 file(s) modified)</div><div>Adapting minsoc_top.v and minsoc_verilog_files.txt to new names for top modules ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br /> rfajardo Thu, 11 Aug 2011 17:39:35 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=75 or1200.h includes a CLABLE macro which uses __USER_LABEL_PREFIX__(from compiler defined ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=74 <div><strong>Rev 74 - rfajardo</strong> (4 file(s) modified)</div><div>or1200.h includes a CLABLE macro which uses __USER_LABEL_PREFIX__(from compiler defined ...</div>~ /minsoc/trunk/sw/support/common.mk<br />~ /minsoc/trunk/sw/support/except.S<br />~ /minsoc/trunk/sw/support/or1200.h<br />~ /minsoc/trunk/sw/support/reset.S<br /> rfajardo Tue, 10 May 2011 19:06:26 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=74 Makefile does not automatic clean anymore. In Windows rm -f ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=73 <div><strong>Rev 73 - rfajardo</strong> (5 file(s) modified)</div><div>Makefile does not automatic clean anymore. In Windows rm -f ...</div>~ /minsoc/trunk/sim/modelsim/compile_design.bat<br />~ /minsoc/trunk/sim/modelsim/prepare_modelsim.bat<br />~ /minsoc/trunk/sim/modelsim/run_sim.bat<br />+ /minsoc/trunk/syn/setup.bat<br />~ /minsoc/trunk/syn/src/Makefile<br /> rfajardo Tue, 10 May 2011 13:52:00 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=73 Adding Windows batch files to run a Modelsim simulation. ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=72 <div><strong>Rev 72 - rfajardo</strong> (3 file(s) modified)</div><div>Adding Windows batch files to run a Modelsim simulation. <br /> ...</div>+ /minsoc/trunk/sim/modelsim/compile_design.bat<br />+ /minsoc/trunk/sim/modelsim/prepare_modelsim.bat<br />+ /minsoc/trunk/sim/modelsim/run_sim.bat<br /> rfajardo Tue, 10 May 2011 12:50:07 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=72 Modelsim whines about missing timescales: -minsoc_bench.v, minsoc_memory_model.v and ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=71 <div><strong>Rev 71 - rfajardo</strong> (3 file(s) modified)</div><div>Modelsim whines about missing timescales: <br /> -minsoc_bench.v, minsoc_memory_model.v and ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_memory_model.v<br />~ /minsoc/trunk/bench/verilog/vpi/dbg_comm_vpi.v<br /> rfajardo Tue, 10 May 2011 10:34:10 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=71 Including a global timescale under minsoc/rtl/verilog to control simulation. It ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=70 <div><strong>Rev 70 - rfajardo</strong> (10 file(s) modified)</div><div>Including a global timescale under minsoc/rtl/verilog to control simulation. It ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/std/minsoc_bench_defines.v<br />+ /minsoc/trunk/rtl/verilog/timescale.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />+ /minsoc/trunk/sim/modelsim<br />+ /minsoc/trunk/sim/modelsim/compile_design.sh<br />+ /minsoc/trunk/sim/modelsim/prepare_modelsim.sh<br />+ /minsoc/trunk/sim/modelsim/run_sim.sh<br /> rfajardo Tue, 10 May 2011 10:06:07 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=70 backend update: -minsoc_bench_defines.v ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=69 <div><strong>Rev 69 - rfajardo</strong> (21 file(s) modified)</div><div>backend update: <br /> -minsoc_bench_defines.v<br /> ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/gcc-opt.mk<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/gcc-opt.mk<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/board.h<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/gcc-opt.mk<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/or1200_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/orp.ld<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/spartan3e_starter_kit_eth.ucf<br />~ /minsoc/trunk/backend/std/configure<br />+ /minsoc/trunk/backend/std/gcc-opt.mk<br />+ /minsoc/trunk/backend/std/minsoc_bench_defines.v<br />- /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />~ /minsoc/trunk/sw/support/Makefile.inc<br /> rfajardo Thu, 05 May 2011 18:11:35 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=69 Still one configuration mismatch on minsoc_defines.v: -MEMORY_ADR_WIDTH ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=68 <div><strong>Rev 68 - rfajardo</strong> (1 file(s) modified)</div><div>Still one configuration mismatch on minsoc_defines.v:<br /> -MEMORY_ADR_WIDTH ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_defines.v<br /> rfajardo Tue, 03 May 2011 14:25:40 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=68 Constraint file for backend spartan3a_dsp_kit.ucf was configured to include the ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=67 <div><strong>Rev 67 - rfajardo</strong> (1 file(s) modified)</div><div>Constraint file for backend spartan3a_dsp_kit.ucf was configured to include the ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf<br /> rfajardo Tue, 03 May 2011 14:17:59 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2F&rev=67
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