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https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&
Fri, 29 Mar 2024 09:04:19 +0100FeedCreator 1.7.2Installation on Ubuntu-11.10 has shown that a binary called makeinfo ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=136
<div><strong>Rev 136 - rfajardo</strong> (1 file(s) modified)</div><div>Installation on Ubuntu-11.10 has shown that a binary called makeinfo ...</div>~ /minsoc/branches/rc-1.0/utils/setup/minsoc-install.sh<br />rfajardoMon, 14 Nov 2011 15:14:41 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=136run_sim.bat for ModelSim updated to acquire the firmware_size for command ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=134
<div><strong>Rev 134 - rfajardo</strong> (1 file(s) modified)</div><div>run_sim.bat for ModelSim updated to acquire the firmware_size for command ...</div>~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.bat<br />rfajardoMon, 07 Nov 2011 11:14:41 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=134Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=133
<div><strong>Rev 133 - rfajardo</strong> (7 file(s) modified)</div><div>Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock ...</div>+ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_core.v<br />~ /minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj<br />~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.bat<br />~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.sh<br />~ /minsoc/branches/rc-1.0/sim/run/run_bench<br />~ /minsoc/branches/rc-1.0/sw/utils/bin2hex.c<br />rfajardoMon, 07 Nov 2011 09:48:11 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=133ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=132
<div><strong>Rev 132 - rfajardo</strong> (2 file(s) modified)</div><div>ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench.</div>~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.bat<br />~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.sh<br />rfajardoThu, 03 Nov 2011 14:10:18 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=132Renaming testbench modules. Adding to ifdefs without which the testbench ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=131
<div><strong>Rev 131 - rfajardo</strong> (4 file(s) modified)</div><div>Renaming testbench modules. Adding to ifdefs without which the testbench ...</div>- /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_clock.v<br />+ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_core.v<br />~ /minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj<br />rfajardoThu, 03 Nov 2011 13:58:53 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=131minsoc_bench.v: task test_eth has to be phased out together with ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=130
<div><strong>Rev 130 - rfajardo</strong> (1 file(s) modified)</div><div>minsoc_bench.v: task test_eth has to be phased out together with ...</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />rfajardoThu, 03 Nov 2011 11:39:30 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=130Removing bugs introduced when splitting clocks and reset.
...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=129
<div><strong>Rev 129 - rfajardo</strong> (2 file(s) modified)</div><div>Removing bugs introduced when splitting clocks and reset. <br />
...</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_clock.v<br />rfajardoThu, 03 Nov 2011 00:31:18 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=129Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=128
<div><strong>Rev 128 - rfajardo</strong> (3 file(s) modified)</div><div>Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v.</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />+ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_clock.v<br />~ /minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj<br />rfajardoWed, 02 Nov 2011 23:46:04 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=128Removing redundant simulation output.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=127
<div><strong>Rev 127 - rfajardo</strong> (1 file(s) modified)</div><div>Removing redundant simulation output.</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />rfajardoWed, 02 Nov 2011 17:38:45 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=127Updating information about simulation time for Ethernet test.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=126
<div><strong>Rev 126 - rfajardo</strong> (1 file(s) modified)</div><div>Updating information about simulation time for Ethernet test.</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />rfajardoWed, 02 Nov 2011 17:36:33 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=126Adjusting testbench messages. Creating tasks for firmware tests.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=125
<div><strong>Rev 125 - rfajardo</strong> (1 file(s) modified)</div><div>Adjusting testbench messages. Creating tasks for firmware tests.</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />rfajardoWed, 02 Nov 2011 17:19:19 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=125Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=124
<div><strong>Rev 124 - rfajardo</strong> (6 file(s) modified)</div><div>Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart ...</div>~ /minsoc/branches/rc-1.0/backend/altera_3c25_board/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/std/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />rfajardoWed, 02 Nov 2011 15:27:24 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=124Renaming reg final to firmware_size. Final is a keyword for ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=123
<div><strong>Rev 123 - rfajardo</strong> (1 file(s) modified)</div><div>Renaming reg final to firmware_size. Final is a keyword for ...</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />rfajardoWed, 02 Nov 2011 10:39:00 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=123Renaming minsoc-configure.sh to minsoc-setup.sh.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=122
<div><strong>Rev 122 - rfajardo</strong> (2 file(s) modified)</div><div>Renaming minsoc-configure.sh to minsoc-setup.sh.</div>- /minsoc/branches/rc-1.0/utils/setup/minsoc-configure.sh<br />+ /minsoc/branches/rc-1.0/utils/setup/minsoc-setup.sh<br />rfajardoThu, 27 Oct 2011 21:12:31 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=122Asserting svn:executable properties of modelsim/*.bat scripts.
Including corrected patch for ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=121
<div><strong>Rev 121 - rfajardo</strong> (7 file(s) modified)</div><div>Asserting svn:executable properties of modelsim/*.bat scripts. <br />
<br />
Including corrected patch for ...</div>~ /minsoc/branches/rc-1.0/sim/modelsim/compile_design.bat<br />~ /minsoc/branches/rc-1.0/sim/modelsim/prepare_modelsim.bat<br />~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.bat<br />~ /minsoc/branches/rc-1.0/syn/xilinx/setup.bat<br />~ /minsoc/branches/rc-1.0/utils/setup/configure.sh<br />+ /minsoc/branches/rc-1.0/utils/setup/or1200v1_hwbkpt.patch<br />~ /minsoc/branches/rc-1.0/utils/setup/required-cygwin-tools.txt<br />rfajardoThu, 27 Oct 2011 19:39:23 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=121ethmac.prj: a file was missing
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=120
<div><strong>Rev 120 - rfajardo</strong> (1 file(s) modified)</div><div>ethmac.prj: a file was missing</div>~ /minsoc/branches/rc-1.0/prj/src/ethmac.prj<br />rfajardoThu, 27 Oct 2011 16:49:07 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=120Tricking Subversion to accept bat files that are now executable.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=119
<div><strong>Rev 119 - rfajardo</strong> (4 file(s) modified)</div><div>Tricking Subversion to accept bat files that are now executable.</div>~ /minsoc/branches/rc-1.0/sim/modelsim/compile_design.bat<br />~ /minsoc/branches/rc-1.0/sim/modelsim/prepare_modelsim.bat<br />~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.bat<br />~ /minsoc/branches/rc-1.0/syn/xilinx/setup.bat<br />rfajardoThu, 27 Oct 2011 16:19:08 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=119Configure scripts for Xilinx devices updated. All of them require ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=118
<div><strong>Rev 118 - rfajardo</strong> (4 file(s) modified)</div><div>Configure scripts for Xilinx devices updated. All of them require ...</div>~ /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/configure<br />+ /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/or1200_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/configure<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit_eth/configure<br />rfajardoThu, 27 Oct 2011 16:16:18 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=118spartan3e_starter_kit designs require DUALPORT from or1200_defines.v to be active instead ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=117
<div><strong>Rev 117 - rfajardo</strong> (2 file(s) modified)</div><div>spartan3e_starter_kit designs require DUALPORT from or1200_defines.v to be active instead ...</div>~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/or1200_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit_eth/or1200_defines.v<br />rfajardoThu, 27 Oct 2011 15:27:12 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=117Configure scripts were trying to copy/patch projects files before creating ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=116
<div><strong>Rev 116 - rfajardo</strong> (5 file(s) modified)</div><div>Configure scripts were trying to copy/patch projects files before creating ...</div>~ /minsoc/branches/rc-1.0/backend/altera_3c25_board/configure<br />~ /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/configure<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/branches/rc-1.0/backend/std/configure<br />rfajardoThu, 27 Oct 2011 14:53:51 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2F&rev=116