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https://opencores.org/ocsvn/minsoc/minsoc/trunk
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minsoc
WebSVN RSS feed - minsoc
https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fprj%2F&
Mon, 13 Apr 2026 18:14:58 +0100
FeedCreator 1.7.2
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ethmac.prj: a file was missing
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fprj%2F&rev=120
<div><strong>Rev 120 - rfajardo</strong> (1 file(s) modified)</div><div>ethmac.prj: a file was missing</div>~ /minsoc/branches/rc-1.0/prj/src/ethmac.prj<br />
rfajardo
Thu, 27 Oct 2011 16:49:07 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fprj%2F&rev=120
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minsoc-install.sh & minsoc-configure.sh:
-aware of location ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fprj%2F&rev=113
<div><strong>Rev 113 - rfajardo</strong> (7 file(s) modified)</div><div>minsoc-install.sh & minsoc-configure.sh: <br />
-aware of location ...</div>~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/or1200_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit_eth/or1200_defines.v<br />~ /minsoc/branches/rc-1.0/prj/Makefile<br />~ /minsoc/branches/rc-1.0/prj/src/blackboxes/or1200_top.v<br />~ /minsoc/branches/rc-1.0/utils/setup/configure.sh<br />~ /minsoc/branches/rc-1.0/utils/setup/minsoc-configure.sh<br />~ /minsoc/branches/rc-1.0/utils/setup/minsoc-install.sh<br />
rfajardo
Thu, 27 Oct 2011 13:49:07 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fprj%2F&rev=113
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Fixing several minor issues with the system:
...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fprj%2F&rev=110
<div><strong>Rev 110 - rfajardo</strong> (13 file(s) modified)</div><div>Fixing several minor issues with the system:<br />
...</div>~ /minsoc/branches/rc-1.0/backend/altera_3c25_board/configure<br />~ /minsoc/branches/rc-1.0/prj/Makefile<br />- /minsoc/branches/rc-1.0/prj/scripts/altprj.sh<br />+ /minsoc/branches/rc-1.0/prj/scripts/altvhdprj.sh<br />+ /minsoc/branches/rc-1.0/prj/scripts/altvprj.sh<br />~ /minsoc/branches/rc-1.0/prj/scripts/simverilog.sh<br />~ /minsoc/branches/rc-1.0/prj/scripts/simvhdl.sh<br />~ /minsoc/branches/rc-1.0/prj/scripts/xilinxprj.sh<br />~ /minsoc/branches/rc-1.0/prj/src/or1200_top.prj<br />~ /minsoc/branches/rc-1.0/rtl/verilog<br />+ /minsoc/branches/rc-1.0/utils/setup/configure.sh<br />+ /minsoc/branches/rc-1.0/utils/setup/minsoc-configure.sh<br />~ /minsoc/branches/rc-1.0/utils/setup/minsoc-install.sh<br />
rfajardo
Wed, 26 Oct 2011 21:41:05 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fprj%2F&rev=110
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Creating a branche for release candidate 1.0.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fprj%2F&rev=109
<div><strong>Rev 109 - rfajardo</strong> (1 file(s) modified)</div><div>Creating a branche for release candidate 1.0.</div>+ /minsoc/branches/rc-1.0<br />
rfajardo
Wed, 26 Oct 2011 19:51:48 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fprj%2F&rev=109
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Scripts updates to correct paths when working under Windows. Now, ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=108
<div><strong>Rev 108 - rfajardo</strong> (4 file(s) modified)</div><div>Scripts updates to correct paths when working under Windows. Now, ...</div>~ /minsoc/trunk/prj/scripts/simverilog.sh<br />~ /minsoc/trunk/prj/scripts/simvhdl.sh<br />~ /minsoc/trunk/prj/scripts/xilinxprj.sh<br />~ /minsoc/trunk/prj/scripts/xilinxxst.sh<br />
rfajardo
Wed, 26 Oct 2011 16:48:51 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=108
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Adding setup batch script for Altera synthesis on Windows.
prj/scripts/altprj.sh ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=107
<div><strong>Rev 107 - rfajardo</strong> (2 file(s) modified)</div><div>Adding setup batch script for Altera synthesis on Windows. <br />
<br />
prj/scripts/altprj.sh ...</div>~ /minsoc/trunk/prj/scripts/altprj.sh<br />+ /minsoc/trunk/syn/altera/setup.bat<br />
rfajardo
Wed, 26 Oct 2011 13:49:41 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=107
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Enabling modelsim simulation for current project definition.
vhdl and verilog projects ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=104
<div><strong>Rev 104 - rfajardo</strong> (7 file(s) modified)</div><div>Enabling modelsim simulation for current project definition.<br />
vhdl and verilog projects ...</div>~ /minsoc/trunk/prj/Makefile<br />- /minsoc/trunk/prj/scripts/simprj.sh<br />+ /minsoc/trunk/prj/scripts/simverilog.sh<br />+ /minsoc/trunk/prj/scripts/simvhdl.sh<br />~ /minsoc/trunk/sim/modelsim/compile_design.bat<br />~ /minsoc/trunk/sim/modelsim/compile_design.sh<br />~ /minsoc/trunk/sim/run/generate_bench<br />
rfajardo
Wed, 19 Oct 2011 10:31:39 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=104
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As proposed by Javier Almansa automatically generated project files for ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=97
<div><strong>Rev 97 - rfajardo</strong> (32 file(s) modified)</div><div>As proposed by Javier Almansa automatically generated project files for ...</div>~ /minsoc/trunk/backend/altera_3c25_board/configure<br />~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/trunk/backend/std/configure<br />- /minsoc/trunk/prj/altera/adbg_top.prj<br />- /minsoc/trunk/prj/altera/altera_virtual_jtag.prj<br />- /minsoc/trunk/prj/altera/ethmac.prj<br />- /minsoc/trunk/prj/altera/jtag_top.prj<br />- /minsoc/trunk/prj/altera/minsoc_bench.prj<br />- /minsoc/trunk/prj/altera/minsoc_top.prj<br />- /minsoc/trunk/prj/altera/or1200_top.prj<br />- /minsoc/trunk/prj/altera/uart_top.prj<br />- /minsoc/trunk/prj/sim/adbg_top.src<br />- /minsoc/trunk/prj/sim/ethmac.src<br />- /minsoc/trunk/prj/sim/jtag_top.src<br />- /minsoc/trunk/prj/sim/minsoc.src<br />- /minsoc/trunk/prj/sim/minsoc_top.src<br />- /minsoc/trunk/prj/sim/or1200_top.src<br />- /minsoc/trunk/prj/sim/uart_top.src<br />- /minsoc/trunk/prj/xilinx/adbg_top.prj<br />- /minsoc/trunk/prj/xilinx/adbg_top.xst<br />- /minsoc/trunk/prj/xilinx/ethmac.prj<br />- /minsoc/trunk/prj/xilinx/ethmac.xst<br />- /minsoc/trunk/prj/xilinx/jtag_top.prj<br />- /minsoc/trunk/prj/xilinx/jtag_top.xst<br />- /minsoc/trunk/prj/xilinx/minsoc_top.prj<br />- /minsoc/trunk/prj/xilinx/minsoc_top.xst<br />- /minsoc/trunk/prj/xilinx/or1200_top.prj<br />- /minsoc/trunk/prj/xilinx/or1200_top.xst<br />- /minsoc/trunk/prj/xilinx/uart_top.prj<br />- /minsoc/trunk/prj/xilinx/uart_top.xst<br />
rfajardo
Mon, 12 Sep 2011 08:54:47 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=97
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Some files needed for Altera synthesis
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=96
<div><strong>Rev 96 - javieralso</strong> (5 file(s) modified)</div><div>Some files needed for Altera synthesis</div>~ /minsoc/trunk/backend/altera_3c25_board/configure<br />+ /minsoc/trunk/prj/altera/altera_virtual_jtag.prj<br />~ /minsoc/trunk/prj/Makefile<br />+ /minsoc/trunk/prj/scripts/altprj.sh<br />+ /minsoc/trunk/prj/src/altera_virtual_jtag.prj<br />
javieralso
Sun, 11 Sep 2011 22:08:57 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=96
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Makefile for Altera FPGAs fixed
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=95
<div><strong>Rev 95 - javieralso</strong> (17 file(s) modified)</div><div>Makefile for Altera FPGAs fixed</div>~ /minsoc/trunk/backend/altera_3c25_board/configure<br />~ /minsoc/trunk/backend/altera_3c25_board/minsoc_defines.v<br />+ /minsoc/trunk/prj/altera/adbg_top.prj<br />- /minsoc/trunk/prj/altera/adv_dbg.prj<br />- /minsoc/trunk/prj/altera/altera_jtag.prj<br />/minsoc/trunk/prj/altera/ethmac.prj<br />+ /minsoc/trunk/prj/altera/jtag_top.prj<br />+ /minsoc/trunk/prj/altera/minsoc_bench.prj<br />/minsoc/trunk/prj/altera/minsoc_top.prj<br />- /minsoc/trunk/prj/altera/minsoc_top.qsf<br />- /minsoc/trunk/prj/altera/or1k.prj<br />+ /minsoc/trunk/prj/altera/or1200_top.prj<br />- /minsoc/trunk/prj/altera/uart16550.prj<br />+ /minsoc/trunk/prj/altera/uart_top.prj<br />~ /minsoc/trunk/prj/Makefile<br />~ /minsoc/trunk/syn/altera/Makefile<br />+ /minsoc/trunk/syn/altera/minsoc_top.qsf<br />
javieralso
Sat, 10 Sep 2011 19:03:56 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=95
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Fix bug in minsoc_top.prj for Altera synthesis
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=94
<div><strong>Rev 94 - javieralso</strong> (1 file(s) modified)</div><div>Fix bug in minsoc_top.prj for Altera synthesis</div>~ /minsoc/trunk/prj/altera/minsoc_top.prj<br />
javieralso
Thu, 08 Sep 2011 10:22:37 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=94
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Support for Altera synthesis. It needs some tune, but it ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=93
<div><strong>Rev 93 - javieralso</strong> (17 file(s) modified)</div><div>Support for Altera synthesis. It needs some tune, but it ...</div>+ /minsoc/trunk/backend/altera_3c25_board<br />+ /minsoc/trunk/backend/altera_3c25_board/altera_3c25_board.ucf<br />+ /minsoc/trunk/backend/altera_3c25_board/board.h<br />+ /minsoc/trunk/backend/altera_3c25_board/configure<br />+ /minsoc/trunk/backend/altera_3c25_board/gcc-opt.mk<br />+ /minsoc/trunk/backend/altera_3c25_board/minsoc_bench_defines.v<br />+ /minsoc/trunk/backend/altera_3c25_board/minsoc_defines.v<br />+ /minsoc/trunk/backend/altera_3c25_board/orp.ld<br />+ /minsoc/trunk/prj/altera/adv_dbg.prj<br />+ /minsoc/trunk/prj/altera/altera_jtag.prj<br />+ /minsoc/trunk/prj/altera/ethmac.prj<br />+ /minsoc/trunk/prj/altera/minsoc_top.prj<br />+ /minsoc/trunk/prj/altera/minsoc_top.qsf<br />+ /minsoc/trunk/prj/altera/or1k.prj<br />+ /minsoc/trunk/prj/altera/uart16550.prj<br />+ /minsoc/trunk/syn/altera<br />+ /minsoc/trunk/syn/altera/Makefile<br />
javieralso
Thu, 08 Sep 2011 07:33:25 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=93
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prj/scripts/: Changing scripts not to include multiple timescale.v files from ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=91
<div><strong>Rev 91 - rfajardo</strong> (5 file(s) modified)</div><div>prj/scripts/: Changing scripts not to include multiple timescale.v files from ...</div>~ /minsoc/trunk/prj/scripts/simprj.sh<br />~ /minsoc/trunk/prj/scripts/xilinxprj.sh<br />~ /minsoc/trunk/prj/sim/minsoc.src<br />~ /minsoc/trunk/prj/sim/minsoc_top.src<br />~ /minsoc/trunk/prj/xilinx/minsoc_top.prj<br />
rfajardo
Wed, 07 Sep 2011 08:47:21 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=91
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After minsoc_top.prj update, make regenerated src and xst files.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=90
<div><strong>Rev 90 - rfajardo</strong> (3 file(s) modified)</div><div>After minsoc_top.prj update, make regenerated src and xst files.</div>~ /minsoc/trunk/prj/sim/minsoc.src<br />~ /minsoc/trunk/prj/sim/minsoc_top.src<br />~ /minsoc/trunk/prj/xilinx/minsoc_top.xst<br />
rfajardo
Tue, 06 Sep 2011 17:17:27 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=90
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minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=89
<div><strong>Rev 89 - rfajardo</strong> (1 file(s) modified)</div><div>minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had ...</div>~ /minsoc/trunk/prj/src/minsoc_top.prj<br />
rfajardo
Tue, 06 Sep 2011 17:10:28 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=89
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Project structure, Xilinx Makefiles and simulation working.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=88
<div><strong>Rev 88 - rfajardo</strong> (20 file(s) modified)</div><div>Project structure, Xilinx Makefiles and simulation working.</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_defines.v<br />~ /minsoc/trunk/prj/Makefile<br />~ /minsoc/trunk/prj/scripts/simprj.sh<br />~ /minsoc/trunk/prj/scripts/xilinxprj.sh<br />~ /minsoc/trunk/prj/scripts/xilinxxst.sh<br />~ /minsoc/trunk/prj/sim/minsoc.src<br />~ /minsoc/trunk/prj/sim/minsoc_top.src<br />+ /minsoc/trunk/prj/src/minsoc_bench.prj<br />~ /minsoc/trunk/prj/src/minsoc_top.prj<br />~ /minsoc/trunk/prj/xilinx/adbg_top.xst<br />~ /minsoc/trunk/prj/xilinx/ethmac.xst<br />~ /minsoc/trunk/prj/xilinx/jtag_top.xst<br />~ /minsoc/trunk/prj/xilinx/minsoc_top.prj<br />~ /minsoc/trunk/prj/xilinx/minsoc_top.xst<br />~ /minsoc/trunk/prj/xilinx/or1200_top.xst<br />~ /minsoc/trunk/prj/xilinx/uart_top.xst<br />~ /minsoc/trunk/rtl/verilog/xilinx_dcm.v<br />~ /minsoc/trunk/syn/xilinx/Makefile<br />
rfajardo
Tue, 06 Sep 2011 16:54:44 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=88
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Central project definition under prj. Synthesis and simulation take their ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=85
<div><strong>Rev 85 - rfajardo</strong> (55 file(s) modified)</div><div>Central project definition under prj. Synthesis and simulation take their ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/trunk/backend/std/configure<br />+ /minsoc/trunk/prj<br />+ /minsoc/trunk/prj/altera<br />+ /minsoc/trunk/prj/Makefile<br />+ /minsoc/trunk/prj/scripts<br />+ /minsoc/trunk/prj/scripts/simprj.sh<br />+ /minsoc/trunk/prj/scripts/xilinxprj.sh<br />+ /minsoc/trunk/prj/scripts/xilinxxst.sh<br />+ /minsoc/trunk/prj/sim<br />+ /minsoc/trunk/prj/sim/adbg_top.src<br />+ /minsoc/trunk/prj/sim/ethmac.src<br />+ /minsoc/trunk/prj/sim/jtag_top.src<br />+ /minsoc/trunk/prj/sim/minsoc.src<br />+ /minsoc/trunk/prj/sim/minsoc_top.src<br />+ /minsoc/trunk/prj/sim/or1200_top.src<br />+ /minsoc/trunk/prj/sim/uart_top.src<br />+ /minsoc/trunk/prj/src<br />+ /minsoc/trunk/prj/src/adbg_top.prj<br />+ /minsoc/trunk/prj/src/blackboxes<br />+ /minsoc/trunk/prj/src/blackboxes/ethmac.v<br />- /minsoc/trunk/prj/src/blackboxes/eth_top.v<br />+ /minsoc/trunk/prj/src/ethmac.prj<br />+ /minsoc/trunk/prj/src/jtag_top.prj<br />+ /minsoc/trunk/prj/src/minsoc_top.prj<br />+ /minsoc/trunk/prj/src/or1200_top.prj<br />+ /minsoc/trunk/prj/src/uart_top.prj<br />+ /minsoc/trunk/prj/xilinx<br />+ /minsoc/trunk/prj/xilinx/adbg_top.prj<br />+ /minsoc/trunk/prj/xilinx/adbg_top.xst<br />+ /minsoc/trunk/prj/xilinx/ethmac.prj<br />+ /minsoc/trunk/prj/xilinx/ethmac.xst<br />+ /minsoc/trunk/prj/xilinx/jtag_top.prj<br />+ /minsoc/trunk/prj/xilinx/jtag_top.xst<br />+ /minsoc/trunk/prj/xilinx/minsoc_top.prj<br />+ /minsoc/trunk/prj/xilinx/minsoc_top.xst<br />+ /minsoc/trunk/prj/xilinx/or1200_top.prj<br />+ /minsoc/trunk/prj/xilinx/or1200_top.xst<br />+ /minsoc/trunk/prj/xilinx/uart_top.prj<br />+ /minsoc/trunk/prj/xilinx/uart_top.xst<br />- /minsoc/trunk/sim/bin<br />~ /minsoc/trunk/sim/modelsim/compile_design.bat<br />~ /minsoc/trunk/sim/modelsim/compile_design.sh<br />~ /minsoc/trunk/sim/run/generate_bench<br />- /minsoc/trunk/syn/blackboxes<br />- /minsoc/trunk/syn/buildSupport/adbg_top.prj<br />- /minsoc/trunk/syn/buildSupport/eth_top.prj<br />- /minsoc/trunk/syn/buildSupport/minsoc_top.prj<br />- /minsoc/trunk/syn/buildSupport/or1200_top.prj<br />- /minsoc/trunk/syn/buildSupport/uart_top.prj<br />- /minsoc/trunk/syn/src<br />+ /minsoc/trunk/syn/xilinx<br />+ /minsoc/trunk/syn/xilinx/Makefile<br />
rfajardo
Tue, 06 Sep 2011 15:34:18 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2F&rev=85
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