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minsoc
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https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fsim%2Fmodelsim%2Frun_sim.sh&
Fri, 29 Mar 2024 12:55:43 +0100
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Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fsim%2Fmodelsim%2F&rev=133
<div><strong>Rev 133 - rfajardo</strong> (7 file(s) modified)</div><div>Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock ...</div>+ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_core.v<br />~ /minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj<br />~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.bat<br />~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.sh<br />~ /minsoc/branches/rc-1.0/sim/run/run_bench<br />~ /minsoc/branches/rc-1.0/sw/utils/bin2hex.c<br />
rfajardo
Mon, 07 Nov 2011 09:48:11 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fsim%2Fmodelsim%2F&rev=133
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ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fsim%2Fmodelsim%2F&rev=132
<div><strong>Rev 132 - rfajardo</strong> (2 file(s) modified)</div><div>ModelSim simulation, running top_module minsoc_bench_clock now, instead of minsoc_bench.</div>~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.bat<br />~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.sh<br />
rfajardo
Thu, 03 Nov 2011 14:10:18 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fsim%2Fmodelsim%2F&rev=132
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Creating a branche for release candidate 1.0.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fsim%2Fmodelsim%2F&rev=109
<div><strong>Rev 109 - rfajardo</strong> (1 file(s) modified)</div><div>Creating a branche for release candidate 1.0.</div>+ /minsoc/branches/rc-1.0<br />
rfajardo
Wed, 26 Oct 2011 19:51:48 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fsim%2Fmodelsim%2F&rev=109
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Including a global timescale under minsoc/rtl/verilog to control simulation. It ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fsim%2Fmodelsim%2F&rev=70
<div><strong>Rev 70 - rfajardo</strong> (10 file(s) modified)</div><div>Including a global timescale under minsoc/rtl/verilog to control simulation. It ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/std/minsoc_bench_defines.v<br />+ /minsoc/trunk/rtl/verilog/timescale.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />+ /minsoc/trunk/sim/modelsim<br />+ /minsoc/trunk/sim/modelsim/compile_design.sh<br />+ /minsoc/trunk/sim/modelsim/prepare_modelsim.sh<br />+ /minsoc/trunk/sim/modelsim/run_sim.sh<br />
rfajardo
Tue, 10 May 2011 10:06:07 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fsim%2Fmodelsim%2F&rev=70
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