OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Error creating feed file, please check write permissions.
minsoc WebSVN RSS feed - minsoc https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fbench%2F& Tue, 16 Jun 2026 09:58:17 +0100 FeedCreator 1.7.2 Creating a verilator branche. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fbench%2F&rev=139 <div><strong>Rev 139 - rfajardo</strong> (1 file(s) modified)</div><div>Creating a verilator branche.</div>+ /minsoc/branches/verilator<br /> rfajardo Tue, 22 Nov 2011 10:09:55 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fbench%2F&rev=139 Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=133 <div><strong>Rev 133 - rfajardo</strong> (7 file(s) modified)</div><div>Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock ...</div>+ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_core.v<br />~ /minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj<br />~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.bat<br />~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.sh<br />~ /minsoc/branches/rc-1.0/sim/run/run_bench<br />~ /minsoc/branches/rc-1.0/sw/utils/bin2hex.c<br /> rfajardo Mon, 07 Nov 2011 09:48:11 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=133 Renaming testbench modules. Adding to ifdefs without which the testbench ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=131 <div><strong>Rev 131 - rfajardo</strong> (4 file(s) modified)</div><div>Renaming testbench modules. Adding to ifdefs without which the testbench ...</div>- /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_clock.v<br />+ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_core.v<br />~ /minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj<br /> rfajardo Thu, 03 Nov 2011 13:58:53 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=131 minsoc_bench.v: task test_eth has to be phased out together with ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=130 <div><strong>Rev 130 - rfajardo</strong> (1 file(s) modified)</div><div>minsoc_bench.v: task test_eth has to be phased out together with ...</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br /> rfajardo Thu, 03 Nov 2011 11:39:30 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=130 Removing bugs introduced when splitting clocks and reset. ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=129 <div><strong>Rev 129 - rfajardo</strong> (2 file(s) modified)</div><div>Removing bugs introduced when splitting clocks and reset. <br /> ...</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_clock.v<br /> rfajardo Thu, 03 Nov 2011 00:31:18 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=129 Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=128 <div><strong>Rev 128 - rfajardo</strong> (3 file(s) modified)</div><div>Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v.</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />+ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_clock.v<br />~ /minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj<br /> rfajardo Wed, 02 Nov 2011 23:46:04 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=128 Removing redundant simulation output. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=127 <div><strong>Rev 127 - rfajardo</strong> (1 file(s) modified)</div><div>Removing redundant simulation output.</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br /> rfajardo Wed, 02 Nov 2011 17:38:45 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=127 Updating information about simulation time for Ethernet test. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=126 <div><strong>Rev 126 - rfajardo</strong> (1 file(s) modified)</div><div>Updating information about simulation time for Ethernet test.</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br /> rfajardo Wed, 02 Nov 2011 17:36:33 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=126 Adjusting testbench messages. Creating tasks for firmware tests. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=125 <div><strong>Rev 125 - rfajardo</strong> (1 file(s) modified)</div><div>Adjusting testbench messages. Creating tasks for firmware tests.</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br /> rfajardo Wed, 02 Nov 2011 17:19:19 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=125 Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=124 <div><strong>Rev 124 - rfajardo</strong> (6 file(s) modified)</div><div>Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart ...</div>~ /minsoc/branches/rc-1.0/backend/altera_3c25_board/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/std/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br /> rfajardo Wed, 02 Nov 2011 15:27:24 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=124 Renaming reg final to firmware_size. Final is a keyword for ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=123 <div><strong>Rev 123 - rfajardo</strong> (1 file(s) modified)</div><div>Renaming reg final to firmware_size. Final is a keyword for ...</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br /> rfajardo Wed, 02 Nov 2011 10:39:00 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=123 Creating a branche for release candidate 1.0. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=109 <div><strong>Rev 109 - rfajardo</strong> (1 file(s) modified)</div><div>Creating a branche for release candidate 1.0.</div>+ /minsoc/branches/rc-1.0<br /> rfajardo Wed, 26 Oct 2011 19:51:48 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbench%2F&rev=109 Modelsim whines about missing timescales: -minsoc_bench.v, minsoc_memory_model.v and ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=71 <div><strong>Rev 71 - rfajardo</strong> (3 file(s) modified)</div><div>Modelsim whines about missing timescales: <br /> -minsoc_bench.v, minsoc_memory_model.v and ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_memory_model.v<br />~ /minsoc/trunk/bench/verilog/vpi/dbg_comm_vpi.v<br /> rfajardo Tue, 10 May 2011 10:34:10 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=71 backend update: -minsoc_bench_defines.v ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=69 <div><strong>Rev 69 - rfajardo</strong> (21 file(s) modified)</div><div>backend update: <br /> -minsoc_bench_defines.v<br /> ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/gcc-opt.mk<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/gcc-opt.mk<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/board.h<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/gcc-opt.mk<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/or1200_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/orp.ld<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/spartan3e_starter_kit_eth.ucf<br />~ /minsoc/trunk/backend/std/configure<br />+ /minsoc/trunk/backend/std/gcc-opt.mk<br />+ /minsoc/trunk/backend/std/minsoc_bench_defines.v<br />- /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />~ /minsoc/trunk/sw/support/Makefile.inc<br /> rfajardo Thu, 05 May 2011 18:11:35 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=69 firmware makefiles: -every firmware makefile has now ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=64 <div><strong>Rev 64 - rfajardo</strong> (61 file(s) modified)</div><div>firmware makefiles:<br /> -every firmware makefile has now ...</div>+ /minsoc/trunk/backend/ml509<br />- /minsoc/trunk/backend/ml509.ucf<br />+ /minsoc/trunk/backend/ml509/ml509.ucf<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit<br />- /minsoc/trunk/backend/spartan3a_dsp_kit.ucf<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/board.h<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_defines.v<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/orp.ld<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf<br />+ /minsoc/trunk/backend/spartan3e_starter_kit<br />- /minsoc/trunk/backend/spartan3e_starter_kit.ucf<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/board.h<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/orp.ld<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf<br />+ /minsoc/trunk/backend/std<br />+ /minsoc/trunk/backend/std/board.h<br />+ /minsoc/trunk/backend/std/minsoc_defines.v<br />+ /minsoc/trunk/backend/std/orp.ld<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />- /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />~ /minsoc/trunk/sw/drivers/can.c<br />+ /minsoc/trunk/sw/drivers/common.mk<br />~ /minsoc/trunk/sw/drivers/eth.c<br />~ /minsoc/trunk/sw/drivers/i2c.c<br />- /minsoc/trunk/sw/drivers/Makefile<br />~ /minsoc/trunk/sw/drivers/uart.c<br />+ /minsoc/trunk/sw/eth/common.mk<br />~ /minsoc/trunk/sw/eth/eth.c<br />- /minsoc/trunk/sw/eth/Makefile<br />- /minsoc/trunk/sw/support/board.h<br />+ /minsoc/trunk/sw/support/common.mk<br />/minsoc/trunk/sw/support/Makefile<br />~ /minsoc/trunk/sw/support/Makefile.inc<br />- /minsoc/trunk/sw/support/orp.ld<br />~ /minsoc/trunk/sw/support/reset.S<br />~ /minsoc/trunk/sw/support/tick.c<br />+ /minsoc/trunk/sw/uart/common.mk<br />- /minsoc/trunk/sw/uart/Makefile<br />~ /minsoc/trunk/sw/uart/uart.c<br />- /minsoc/trunk/syn/blackboxes/OR1K_startup_generic.v<br />- /minsoc/trunk/syn/buildSupport/adbg_top.xst<br />- /minsoc/trunk/syn/buildSupport/eth_top.xst<br />- /minsoc/trunk/syn/buildSupport/minsoc_startup_top.prj<br />- /minsoc/trunk/syn/buildSupport/minsoc_startup_top.xst<br />~ /minsoc/trunk/syn/buildSupport/minsoc_top.prj<br />- /minsoc/trunk/syn/buildSupport/minsoc_top.xst<br />- /minsoc/trunk/syn/buildSupport/or1200_top.xst<br />- /minsoc/trunk/syn/buildSupport/uart_top.xst<br />- /minsoc/trunk/syn/Makefile<br />+ /minsoc/trunk/syn/src<br />+ /minsoc/trunk/syn/src/adbg_top.xst<br />+ /minsoc/trunk/syn/src/eth_top.xst<br />+ /minsoc/trunk/syn/src/Makefile<br />+ /minsoc/trunk/syn/src/minsoc_top.xst<br />+ /minsoc/trunk/syn/src/or1200_top.xst<br />+ /minsoc/trunk/syn/src/uart_top.xst<br />- /minsoc/trunk/utils/contributions/.directory<br /> rfajardo Tue, 03 May 2011 11:01:33 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=64 Selection of memory model or implementation memory is now made ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=60 <div><strong>Rev 60 - rfajardo</strong> (8 file(s) modified)</div><div>Selection of memory model or implementation memory is now made ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/bench/verilog/minsoc_memory_model.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />- /minsoc/trunk/sim/bin/minsoc_memory.txt<br />- /minsoc/trunk/sim/bin/minsoc_model.txt<br />+ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />~ /minsoc/trunk/sim/run/generate_bench<br /> rfajardo Thu, 28 Apr 2011 22:44:09 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=60 undefinition of NEGATIVE_RESET on minsoc_bench_defines.v cannot affect other inclusions of ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=59 <div><strong>Rev 59 - rfajardo</strong> (2 file(s) modified)</div><div>undefinition of NEGATIVE_RESET on minsoc_bench_defines.v cannot affect other inclusions of ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br /> rfajardo Thu, 28 Apr 2011 21:59:30 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=59 Standard definitions depended on implementation order. Now, this should be ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=58 <div><strong>Rev 58 - rfajardo</strong> (2 file(s) modified)</div><div>Standard definitions depended on implementation order. Now, this should be ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br /> rfajardo Thu, 28 Apr 2011 21:50:11 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=58 1) Period calculations through 1/freq on testbench use now a ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=28 <div><strong>Rev 28 - rfajardo</strong> (4 file(s) modified)</div><div>1) Period calculations through 1/freq on testbench use now a ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/doc/howto.pdf<br />~ /minsoc/trunk/doc/src/howto.odt<br /> rfajardo Wed, 05 May 2010 14:50:01 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=28 Simulation library fpga_memory_primitives.v had an issue with its lpm_ram_dq module, ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=27 <div><strong>Rev 27 - rfajardo</strong> (1 file(s) modified)</div><div>Simulation library fpga_memory_primitives.v had an issue with its lpm_ram_dq module, ...</div>~ /minsoc/trunk/bench/verilog/sim_lib/fpga_memory_primitives.v<br /> rfajardo Tue, 20 Apr 2010 14:14:15 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=27
© copyright 1999-2026 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.