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minsoc WebSVN RSS feed - minsoc https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F& Tue, 19 Mar 2024 04:26:19 +0100 FeedCreator 1.7.2 Including required modules for verilator simulation. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=140 <div><strong>Rev 140 - rfajardo</strong> (7 file(s) modified)</div><div>Including required modules for verilator simulation.</div>+ /minsoc/branches/verilator/bench/verilator<br />+ /minsoc/branches/verilator/bench/verilator/minsoc_bench_core.v<br />+ /minsoc/branches/verilator/bench/verilator/verilator_defines.v<br />~ /minsoc/branches/verilator/rtl/verilog/minsoc_top.v<br />+ /minsoc/branches/verilator/sim/verilator<br />+ /minsoc/branches/verilator/sim/verilator/generate_verilator_bench<br />+ /minsoc/branches/verilator/sim/verilator/run_verilator_bench<br /> rfajardo Tue, 22 Nov 2011 10:11:38 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=140 Creating a verilator branche. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=139 <div><strong>Rev 139 - rfajardo</strong> (1 file(s) modified)</div><div>Creating a verilator branche.</div>+ /minsoc/branches/verilator<br /> rfajardo Tue, 22 Nov 2011 10:09:55 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=139 Fixing several minor issues with the system: ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=110 <div><strong>Rev 110 - rfajardo</strong> (13 file(s) modified)</div><div>Fixing several minor issues with the system:<br /> ...</div>~ /minsoc/branches/rc-1.0/backend/altera_3c25_board/configure<br />~ /minsoc/branches/rc-1.0/prj/Makefile<br />- /minsoc/branches/rc-1.0/prj/scripts/altprj.sh<br />+ /minsoc/branches/rc-1.0/prj/scripts/altvhdprj.sh<br />+ /minsoc/branches/rc-1.0/prj/scripts/altvprj.sh<br />~ /minsoc/branches/rc-1.0/prj/scripts/simverilog.sh<br />~ /minsoc/branches/rc-1.0/prj/scripts/simvhdl.sh<br />~ /minsoc/branches/rc-1.0/prj/scripts/xilinxprj.sh<br />~ /minsoc/branches/rc-1.0/prj/src/or1200_top.prj<br />~ /minsoc/branches/rc-1.0/rtl/verilog<br />+ /minsoc/branches/rc-1.0/utils/setup/configure.sh<br />+ /minsoc/branches/rc-1.0/utils/setup/minsoc-configure.sh<br />~ /minsoc/branches/rc-1.0/utils/setup/minsoc-install.sh<br /> rfajardo Wed, 26 Oct 2011 21:41:05 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=110 Creating a branche for release candidate 1.0. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=109 <div><strong>Rev 109 - rfajardo</strong> (1 file(s) modified)</div><div>Creating a branche for release candidate 1.0.</div>+ /minsoc/branches/rc-1.0<br /> rfajardo Wed, 26 Oct 2011 19:51:48 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=109 Project structure, Xilinx Makefiles and simulation working. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=88 <div><strong>Rev 88 - rfajardo</strong> (20 file(s) modified)</div><div>Project structure, Xilinx Makefiles and simulation working.</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_defines.v<br />~ /minsoc/trunk/prj/Makefile<br />~ /minsoc/trunk/prj/scripts/simprj.sh<br />~ /minsoc/trunk/prj/scripts/xilinxprj.sh<br />~ /minsoc/trunk/prj/scripts/xilinxxst.sh<br />~ /minsoc/trunk/prj/sim/minsoc.src<br />~ /minsoc/trunk/prj/sim/minsoc_top.src<br />+ /minsoc/trunk/prj/src/minsoc_bench.prj<br />~ /minsoc/trunk/prj/src/minsoc_top.prj<br />~ /minsoc/trunk/prj/xilinx/adbg_top.xst<br />~ /minsoc/trunk/prj/xilinx/ethmac.xst<br />~ /minsoc/trunk/prj/xilinx/jtag_top.xst<br />~ /minsoc/trunk/prj/xilinx/minsoc_top.prj<br />~ /minsoc/trunk/prj/xilinx/minsoc_top.xst<br />~ /minsoc/trunk/prj/xilinx/or1200_top.xst<br />~ /minsoc/trunk/prj/xilinx/uart_top.xst<br />~ /minsoc/trunk/rtl/verilog/xilinx_dcm.v<br />~ /minsoc/trunk/syn/xilinx/Makefile<br /> rfajardo Tue, 06 Sep 2011 16:54:44 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=88 Adapting minsoc_top.v and minsoc_verilog_files.txt to new names for top modules ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=75 <div><strong>Rev 75 - rfajardo</strong> (2 file(s) modified)</div><div>Adapting minsoc_top.v and minsoc_verilog_files.txt to new names for top modules ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br /> rfajardo Thu, 11 Aug 2011 17:39:35 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=75 Including a global timescale under minsoc/rtl/verilog to control simulation. It ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=70 <div><strong>Rev 70 - rfajardo</strong> (10 file(s) modified)</div><div>Including a global timescale under minsoc/rtl/verilog to control simulation. It ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/std/minsoc_bench_defines.v<br />+ /minsoc/trunk/rtl/verilog/timescale.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />+ /minsoc/trunk/sim/modelsim<br />+ /minsoc/trunk/sim/modelsim/compile_design.sh<br />+ /minsoc/trunk/sim/modelsim/prepare_modelsim.sh<br />+ /minsoc/trunk/sim/modelsim/run_sim.sh<br /> rfajardo Tue, 10 May 2011 10:06:07 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=70 firmware makefiles: -every firmware makefile has now ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=64 <div><strong>Rev 64 - rfajardo</strong> (61 file(s) modified)</div><div>firmware makefiles:<br /> -every firmware makefile has now ...</div>+ /minsoc/trunk/backend/ml509<br />- /minsoc/trunk/backend/ml509.ucf<br />+ /minsoc/trunk/backend/ml509/ml509.ucf<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit<br />- /minsoc/trunk/backend/spartan3a_dsp_kit.ucf<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/board.h<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_defines.v<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/orp.ld<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf<br />+ /minsoc/trunk/backend/spartan3e_starter_kit<br />- /minsoc/trunk/backend/spartan3e_starter_kit.ucf<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/board.h<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/orp.ld<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf<br />+ /minsoc/trunk/backend/std<br />+ /minsoc/trunk/backend/std/board.h<br />+ /minsoc/trunk/backend/std/minsoc_defines.v<br />+ /minsoc/trunk/backend/std/orp.ld<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />- /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />~ /minsoc/trunk/sw/drivers/can.c<br />+ /minsoc/trunk/sw/drivers/common.mk<br />~ /minsoc/trunk/sw/drivers/eth.c<br />~ /minsoc/trunk/sw/drivers/i2c.c<br />- /minsoc/trunk/sw/drivers/Makefile<br />~ /minsoc/trunk/sw/drivers/uart.c<br />+ /minsoc/trunk/sw/eth/common.mk<br />~ /minsoc/trunk/sw/eth/eth.c<br />- /minsoc/trunk/sw/eth/Makefile<br />- /minsoc/trunk/sw/support/board.h<br />+ /minsoc/trunk/sw/support/common.mk<br />/minsoc/trunk/sw/support/Makefile<br />~ /minsoc/trunk/sw/support/Makefile.inc<br />- /minsoc/trunk/sw/support/orp.ld<br />~ /minsoc/trunk/sw/support/reset.S<br />~ /minsoc/trunk/sw/support/tick.c<br />+ /minsoc/trunk/sw/uart/common.mk<br />- /minsoc/trunk/sw/uart/Makefile<br />~ /minsoc/trunk/sw/uart/uart.c<br />- /minsoc/trunk/syn/blackboxes/OR1K_startup_generic.v<br />- /minsoc/trunk/syn/buildSupport/adbg_top.xst<br />- /minsoc/trunk/syn/buildSupport/eth_top.xst<br />- /minsoc/trunk/syn/buildSupport/minsoc_startup_top.prj<br />- /minsoc/trunk/syn/buildSupport/minsoc_startup_top.xst<br />~ /minsoc/trunk/syn/buildSupport/minsoc_top.prj<br />- /minsoc/trunk/syn/buildSupport/minsoc_top.xst<br />- /minsoc/trunk/syn/buildSupport/or1200_top.xst<br />- /minsoc/trunk/syn/buildSupport/uart_top.xst<br />- /minsoc/trunk/syn/Makefile<br />+ /minsoc/trunk/syn/src<br />+ /minsoc/trunk/syn/src/adbg_top.xst<br />+ /minsoc/trunk/syn/src/eth_top.xst<br />+ /minsoc/trunk/syn/src/Makefile<br />+ /minsoc/trunk/syn/src/minsoc_top.xst<br />+ /minsoc/trunk/syn/src/or1200_top.xst<br />+ /minsoc/trunk/syn/src/uart_top.xst<br />- /minsoc/trunk/utils/contributions/.directory<br /> rfajardo Tue, 03 May 2011 11:01:33 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=64 Adding a functional synthesis Makefile system. Still needs a reviews ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=63 <div><strong>Rev 63 - rfajardo</strong> (26 file(s) modified)</div><div>Adding a functional synthesis Makefile system. Still needs a reviews ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit.ucf<br />~ /minsoc/trunk/rtl/verilog/altera_pll.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />+ /minsoc/trunk/syn<br />+ /minsoc/trunk/syn/blackboxes<br />+ /minsoc/trunk/syn/blackboxes/adbg_top.v<br />+ /minsoc/trunk/syn/blackboxes/eth_top.v<br />+ /minsoc/trunk/syn/blackboxes/OR1K_startup_generic.v<br />+ /minsoc/trunk/syn/blackboxes/or1200_top.v<br />+ /minsoc/trunk/syn/blackboxes/uart_top.v<br />+ /minsoc/trunk/syn/buildSupport<br />+ /minsoc/trunk/syn/buildSupport/adbg_top.prj<br />+ /minsoc/trunk/syn/buildSupport/adbg_top.xst<br />+ /minsoc/trunk/syn/buildSupport/eth_top.prj<br />+ /minsoc/trunk/syn/buildSupport/eth_top.xst<br />+ /minsoc/trunk/syn/buildSupport/minsoc_startup_top.prj<br />+ /minsoc/trunk/syn/buildSupport/minsoc_startup_top.xst<br />+ /minsoc/trunk/syn/buildSupport/minsoc_top.prj<br />+ /minsoc/trunk/syn/buildSupport/minsoc_top.xst<br />+ /minsoc/trunk/syn/buildSupport/or1200_top.prj<br />+ /minsoc/trunk/syn/buildSupport/or1200_top.xst<br />+ /minsoc/trunk/syn/buildSupport/uart_top.prj<br />+ /minsoc/trunk/syn/buildSupport/uart_top.xst<br />+ /minsoc/trunk/syn/doc<br />+ /minsoc/trunk/syn/doc/guideTop.pdf<br />+ /minsoc/trunk/syn/Makefile<br /> rfajardo Fri, 29 Apr 2011 17:26:11 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=63 Wrapping different family modules of same manufacturer in a single ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=62 <div><strong>Rev 62 - rfajardo</strong> (4 file(s) modified)</div><div>Wrapping different family modules of same manufacturer in a single ...</div>+ /minsoc/trunk/rtl/verilog/altera_pll.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v<br />- /minsoc/trunk/rtl/verilog/minsoc_pll.v<br />+ /minsoc/trunk/rtl/verilog/xilinx_dcm.v<br /> rfajardo Fri, 29 Apr 2011 10:32:37 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=62 Selection of memory model or implementation memory is now made ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=60 <div><strong>Rev 60 - rfajardo</strong> (8 file(s) modified)</div><div>Selection of memory model or implementation memory is now made ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/bench/verilog/minsoc_memory_model.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />- /minsoc/trunk/sim/bin/minsoc_memory.txt<br />- /minsoc/trunk/sim/bin/minsoc_model.txt<br />+ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />~ /minsoc/trunk/sim/run/generate_bench<br /> rfajardo Thu, 28 Apr 2011 22:44:09 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=60 Standard definitions depended on implementation order. Now, this should be ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=58 <div><strong>Rev 58 - rfajardo</strong> (2 file(s) modified)</div><div>Standard definitions depended on implementation order. Now, this should be ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br /> rfajardo Thu, 28 Apr 2011 21:50:11 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=58 If a FPGA manufacturer is selected, the FPGA families of ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=57 <div><strong>Rev 57 - rfajardo</strong> (1 file(s) modified)</div><div>If a FPGA manufacturer is selected, the FPGA families of ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br /> rfajardo Thu, 28 Apr 2011 21:27:09 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=57 Macros for all Altera family devices and pll instantiation https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=56 <div><strong>Rev 56 - javieralso</strong> (4 file(s) modified)</div><div>Macros for all Altera family devices and pll instantiation</div>~ /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_pll.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br /> javieralso Thu, 21 Apr 2011 22:40:38 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=56 Indentation, deleting redundant files and adding externals https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=53 <div><strong>Rev 53 - ConX.</strong> (29 file(s) modified)</div><div>Indentation, deleting redundant files and adding externals</div>~ /minsoc/trunk/rtl/verilog<br />~ /minsoc/trunk/sw/drivers/can.c<br />~ /minsoc/trunk/sw/drivers/can.h<br />~ /minsoc/trunk/sw/drivers/eth.c<br />~ /minsoc/trunk/sw/drivers/eth.h<br />~ /minsoc/trunk/sw/drivers/i2c.c<br />~ /minsoc/trunk/sw/drivers/i2c.h<br />~ /minsoc/trunk/sw/drivers/interrupts.c<br />~ /minsoc/trunk/sw/drivers/Makefile<br />- /minsoc/trunk/sw/drivers/tick.c<br />- /minsoc/trunk/sw/drivers/tick.h<br />~ /minsoc/trunk/sw/drivers/uart.c<br />~ /minsoc/trunk/sw/drivers/uart.h<br />~ /minsoc/trunk/sw/eth/eth.c<br />~ /minsoc/trunk/sw/support/board.h<br />~ /minsoc/trunk/sw/support/except.S<br />~ /minsoc/trunk/sw/support/int.c<br />~ /minsoc/trunk/sw/support/int.h<br />~ /minsoc/trunk/sw/support/Makefile<br />~ /minsoc/trunk/sw/support/reset.S<br />~ /minsoc/trunk/sw/support/support.c<br />~ /minsoc/trunk/sw/support/support.h<br />+ /minsoc/trunk/sw/support/tick.c<br />+ /minsoc/trunk/sw/support/tick.h<br />- /minsoc/trunk/sw/support/uart.c<br />- /minsoc/trunk/sw/support/uart.h<br />- /minsoc/trunk/sw/support/vfnprintf.c<br />- /minsoc/trunk/sw/support/vfnprintf.h<br />~ /minsoc/trunk/sw/uart/uart.c<br /> ConX. Wed, 20 Apr 2011 11:16:36 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=53 Altera ALTPLL Megafunction Instantiation https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=52 <div><strong>Rev 52 - javieralso</strong> (4 file(s) modified)</div><div>Altera ALTPLL Megafunction Instantiation</div>~ /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_pll.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br /> javieralso Mon, 11 Apr 2011 21:03:29 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=52 Start-up Starter, included in the MinSoC top file, has been ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=33 <div><strong>Rev 33 - rfajardo</strong> (1 file(s) modified)</div><div>Start-up Starter, included in the MinSoC top file, has been ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br /> rfajardo Thu, 07 Oct 2010 13:19:10 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=33 Adaption to or1200_r3. It is still important to change or1200_defines.v: -`define ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=31 <div><strong>Rev 31 - rfajardo</strong> (5 file(s) modified)</div><div>Adaption to or1200_r3. It is still important to change or1200_defines.v:<br /> -`define ...</div>~ /minsoc/trunk/doc/howto.pdf<br />~ /minsoc/trunk/doc/src/howto.odt<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />~ /minsoc/trunk/sim/bin/minsoc_memory.txt<br />~ /minsoc/trunk/sim/bin/minsoc_model.txt<br /> rfajardo Fri, 30 Jul 2010 08:22:31 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=31 On version 34 of the Advanced Debug System the signal ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=26 <div><strong>Rev 26 - rfajardo</strong> (1 file(s) modified)</div><div>On version 34 of the Advanced Debug System the signal ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br /> rfajardo Sun, 11 Apr 2010 01:32:44 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=26 minsoc_defines.v had a semicolon at the end of the two ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=20 <div><strong>Rev 20 - rfajardo</strong> (4 file(s) modified)</div><div>minsoc_defines.v had a semicolon at the end of the two ...</div>~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br /> rfajardo Thu, 21 Jan 2010 13:57:46 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=20
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