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minsoc
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https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2Faltera_pll.v&
Fri, 29 Mar 2024 06:20:25 +0100
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Creating a verilator branche.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=139
<div><strong>Rev 139 - rfajardo</strong> (1 file(s) modified)</div><div>Creating a verilator branche.</div>+ /minsoc/branches/verilator<br />
rfajardo
Tue, 22 Nov 2011 10:09:55 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=139
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Creating a branche for release candidate 1.0.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=109
<div><strong>Rev 109 - rfajardo</strong> (1 file(s) modified)</div><div>Creating a branche for release candidate 1.0.</div>+ /minsoc/branches/rc-1.0<br />
rfajardo
Wed, 26 Oct 2011 19:51:48 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=109
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Adding a functional synthesis Makefile system. Still needs a reviews ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=63
<div><strong>Rev 63 - rfajardo</strong> (26 file(s) modified)</div><div>Adding a functional synthesis Makefile system. Still needs a reviews ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit.ucf<br />~ /minsoc/trunk/rtl/verilog/altera_pll.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />+ /minsoc/trunk/syn<br />+ /minsoc/trunk/syn/blackboxes<br />+ /minsoc/trunk/syn/blackboxes/adbg_top.v<br />+ /minsoc/trunk/syn/blackboxes/eth_top.v<br />+ /minsoc/trunk/syn/blackboxes/OR1K_startup_generic.v<br />+ /minsoc/trunk/syn/blackboxes/or1200_top.v<br />+ /minsoc/trunk/syn/blackboxes/uart_top.v<br />+ /minsoc/trunk/syn/buildSupport<br />+ /minsoc/trunk/syn/buildSupport/adbg_top.prj<br />+ /minsoc/trunk/syn/buildSupport/adbg_top.xst<br />+ /minsoc/trunk/syn/buildSupport/eth_top.prj<br />+ /minsoc/trunk/syn/buildSupport/eth_top.xst<br />+ /minsoc/trunk/syn/buildSupport/minsoc_startup_top.prj<br />+ /minsoc/trunk/syn/buildSupport/minsoc_startup_top.xst<br />+ /minsoc/trunk/syn/buildSupport/minsoc_top.prj<br />+ /minsoc/trunk/syn/buildSupport/minsoc_top.xst<br />+ /minsoc/trunk/syn/buildSupport/or1200_top.prj<br />+ /minsoc/trunk/syn/buildSupport/or1200_top.xst<br />+ /minsoc/trunk/syn/buildSupport/uart_top.prj<br />+ /minsoc/trunk/syn/buildSupport/uart_top.xst<br />+ /minsoc/trunk/syn/doc<br />+ /minsoc/trunk/syn/doc/guideTop.pdf<br />+ /minsoc/trunk/syn/Makefile<br />
rfajardo
Fri, 29 Apr 2011 17:26:11 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=63
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Wrapping different family modules of same manufacturer in a single ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=62
<div><strong>Rev 62 - rfajardo</strong> (4 file(s) modified)</div><div>Wrapping different family modules of same manufacturer in a single ...</div>+ /minsoc/trunk/rtl/verilog/altera_pll.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v<br />- /minsoc/trunk/rtl/verilog/minsoc_pll.v<br />+ /minsoc/trunk/rtl/verilog/xilinx_dcm.v<br />
rfajardo
Fri, 29 Apr 2011 10:32:37 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=62
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Macros for all Altera family devices and pll instantiation
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=56
<div><strong>Rev 56 - javieralso</strong> (4 file(s) modified)</div><div>Macros for all Altera family devices and pll instantiation</div>~ /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_pll.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />
javieralso
Thu, 21 Apr 2011 22:40:38 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=56
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Altera ALTPLL Megafunction Instantiation
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=52
<div><strong>Rev 52 - javieralso</strong> (4 file(s) modified)</div><div>Altera ALTPLL Megafunction Instantiation</div>~ /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_pll.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />
javieralso
Mon, 11 Apr 2011 21:03:29 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=52
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