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minsoc WebSVN RSS feed - minsoc https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2Fminsoc_top.v& Thu, 28 Mar 2024 13:23:59 +0100 FeedCreator 1.7.2 Including required modules for verilator simulation. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=140 <div><strong>Rev 140 - rfajardo</strong> (7 file(s) modified)</div><div>Including required modules for verilator simulation.</div>+ /minsoc/branches/verilator/bench/verilator<br />+ /minsoc/branches/verilator/bench/verilator/minsoc_bench_core.v<br />+ /minsoc/branches/verilator/bench/verilator/verilator_defines.v<br />~ /minsoc/branches/verilator/rtl/verilog/minsoc_top.v<br />+ /minsoc/branches/verilator/sim/verilator<br />+ /minsoc/branches/verilator/sim/verilator/generate_verilator_bench<br />+ /minsoc/branches/verilator/sim/verilator/run_verilator_bench<br /> rfajardo Tue, 22 Nov 2011 10:11:38 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=140 Creating a verilator branche. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=139 <div><strong>Rev 139 - rfajardo</strong> (1 file(s) modified)</div><div>Creating a verilator branche.</div>+ /minsoc/branches/verilator<br /> rfajardo Tue, 22 Nov 2011 10:09:55 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=139 Creating a branche for release candidate 1.0. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=109 <div><strong>Rev 109 - rfajardo</strong> (1 file(s) modified)</div><div>Creating a branche for release candidate 1.0.</div>+ /minsoc/branches/rc-1.0<br /> rfajardo Wed, 26 Oct 2011 19:51:48 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=109 Adapting minsoc_top.v and minsoc_verilog_files.txt to new names for top modules ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=75 <div><strong>Rev 75 - rfajardo</strong> (2 file(s) modified)</div><div>Adapting minsoc_top.v and minsoc_verilog_files.txt to new names for top modules ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br /> rfajardo Thu, 11 Aug 2011 17:39:35 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=75 Selection of memory model or implementation memory is now made ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=60 <div><strong>Rev 60 - rfajardo</strong> (8 file(s) modified)</div><div>Selection of memory model or implementation memory is now made ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/bench/verilog/minsoc_memory_model.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />- /minsoc/trunk/sim/bin/minsoc_memory.txt<br />- /minsoc/trunk/sim/bin/minsoc_model.txt<br />+ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />~ /minsoc/trunk/sim/run/generate_bench<br /> rfajardo Thu, 28 Apr 2011 22:44:09 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=60 Macros for all Altera family devices and pll instantiation https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=56 <div><strong>Rev 56 - javieralso</strong> (4 file(s) modified)</div><div>Macros for all Altera family devices and pll instantiation</div>~ /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_pll.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br /> javieralso Thu, 21 Apr 2011 22:40:38 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=56 Altera ALTPLL Megafunction Instantiation https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=52 <div><strong>Rev 52 - javieralso</strong> (4 file(s) modified)</div><div>Altera ALTPLL Megafunction Instantiation</div>~ /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_pll.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br /> javieralso Mon, 11 Apr 2011 21:03:29 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=52 Start-up Starter, included in the MinSoC top file, has been ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=33 <div><strong>Rev 33 - rfajardo</strong> (1 file(s) modified)</div><div>Start-up Starter, included in the MinSoC top file, has been ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br /> rfajardo Thu, 07 Oct 2010 13:19:10 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=33 Adaption to or1200_r3. It is still important to change or1200_defines.v: -`define ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=31 <div><strong>Rev 31 - rfajardo</strong> (5 file(s) modified)</div><div>Adaption to or1200_r3. It is still important to change or1200_defines.v:<br /> -`define ...</div>~ /minsoc/trunk/doc/howto.pdf<br />~ /minsoc/trunk/doc/src/howto.odt<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />~ /minsoc/trunk/sim/bin/minsoc_memory.txt<br />~ /minsoc/trunk/sim/bin/minsoc_model.txt<br /> rfajardo Fri, 30 Jul 2010 08:22:31 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=31 On version 34 of the Advanced Debug System the signal ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=26 <div><strong>Rev 26 - rfajardo</strong> (1 file(s) modified)</div><div>On version 34 of the Advanced Debug System the signal ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br /> rfajardo Sun, 11 Apr 2010 01:32:44 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=26 minsoc_defines.v had a semicolon at the end of the two ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=20 <div><strong>Rev 20 - rfajardo</strong> (4 file(s) modified)</div><div>minsoc_defines.v had a semicolon at the end of the two ...</div>~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br /> rfajardo Thu, 21 Jan 2010 13:57:46 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=20 Ethernet testbench speed penalty solved. Now Ethernet of testbench and ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=17 <div><strong>Rev 17 - rfajardo</strong> (16 file(s) modified)</div><div>Ethernet testbench speed penalty solved. Now Ethernet of testbench and ...</div>- /minsoc/trunk/bench/verilog/eth_phy.v<br />- /minsoc/trunk/bench/verilog/eth_phy_defines.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/bench/verilog/sim_lib/fpga_memory_primitives.v<br />- /minsoc/trunk/bench/verilog/tb_eth_defines.v<br />~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />+ /minsoc/trunk/sim/bin/minsoc_memory.txt<br />- /minsoc/trunk/sim/bin/minsoc_memory_complete.txt<br />- /minsoc/trunk/sim/bin/minsoc_memory_fast.txt<br />+ /minsoc/trunk/sim/bin/minsoc_model.txt<br />- /minsoc/trunk/sim/bin/minsoc_model_complete.txt<br />- /minsoc/trunk/sim/bin/minsoc_model_fast.txt<br />~ /minsoc/trunk/sim/run/generate_bench<br /> rfajardo Tue, 17 Nov 2009 14:38:49 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=17 Further initialization improvement of non-used signals, setting interrupt signals to ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=16 <div><strong>Rev 16 - rfajardo</strong> (1 file(s) modified)</div><div>Further initialization improvement of non-used signals, setting interrupt signals to ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br /> rfajardo Thu, 12 Nov 2009 11:04:14 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=16 Wishbone error signal of Ethernet core was not tied to ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=14 <div><strong>Rev 14 - rfajardo</strong> (1 file(s) modified)</div><div>Wishbone error signal of Ethernet core was not tied to ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br /> rfajardo Tue, 03 Nov 2009 10:22:29 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=14 Some changes: -wb_cabs removed from minsoc_top.v and ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=7 <div><strong>Rev 7 - rfajardo</strong> (6 file(s) modified)</div><div>Some changes:<br /> -wb_cabs removed from minsoc_top.v and ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_onchip_ram.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_onchip_ram_top.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_tc_top.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br /> rfajardo Fri, 02 Oct 2009 15:56:44 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=7 First commit of project. Beta status: -testbench: ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=2 <div><strong>Rev 2 - rfajardo</strong> (92 file(s) modified)</div><div>First commit of project. Beta status:<br /> -testbench: ...</div>+ /minsoc/trunk/backend<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit.ucf<br />+ /minsoc/trunk/backend/spartan3e_starter_kit.ucf<br />+ /minsoc/trunk/bench<br />+ /minsoc/trunk/bench/verilog<br />+ /minsoc/trunk/bench/verilog/eth_phy.v<br />+ /minsoc/trunk/bench/verilog/eth_phy_defines.v<br />+ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />+ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />+ /minsoc/trunk/bench/verilog/minsoc_memory_model.v<br />+ /minsoc/trunk/bench/verilog/tb_eth_defines.v<br />+ /minsoc/trunk/bench/verilog/vpi<br />+ /minsoc/trunk/bench/verilog/vpi/dbg_comm_vpi.v<br />+ /minsoc/trunk/bench/verilog/vpi/jp-io-vpi.vpi<br />+ /minsoc/trunk/doc<br />+ /minsoc/trunk/doc/lgpl-3.0.txt<br />+ /minsoc/trunk/doc/minsoc.odt<br />+ /minsoc/trunk/doc/minsoc.pdf<br />+ /minsoc/trunk/rtl<br />+ /minsoc/trunk/rtl/verilog<br />+ /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_onchip_ram.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_onchip_ram_top.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/OR1K_startup_generic.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_clgen.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_defines.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_shift.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_top.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_tc_top.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_xilinx_internal_jtag.v<br />+ /minsoc/trunk/sim<br />+ /minsoc/trunk/sim/bin<br />+ /minsoc/trunk/sim/bin/minsoc_memory_complete.txt<br />+ /minsoc/trunk/sim/bin/minsoc_memory_fast.txt<br />+ /minsoc/trunk/sim/bin/minsoc_model_complete.txt<br />+ /minsoc/trunk/sim/bin/minsoc_model_fast.txt<br />+ /minsoc/trunk/sim/results<br />+ /minsoc/trunk/sim/results/wave.do.sav<br />+ /minsoc/trunk/sim/run<br />+ /minsoc/trunk/sim/run/generate_bench<br />+ /minsoc/trunk/sim/run/run_bench<br />+ /minsoc/trunk/sim/run/start_server<br />+ /minsoc/trunk/sw<br />+ /minsoc/trunk/sw/eth<br />+ /minsoc/trunk/sw/eth/eth.c<br />+ /minsoc/trunk/sw/eth/eth.h<br />+ /minsoc/trunk/sw/eth/Makefile<br />+ /minsoc/trunk/sw/support<br />+ /minsoc/trunk/sw/support/board.h<br />+ /minsoc/trunk/sw/support/except.S<br />+ /minsoc/trunk/sw/support/int.c<br />+ /minsoc/trunk/sw/support/int.h<br />+ /minsoc/trunk/sw/support/Makefile<br />+ /minsoc/trunk/sw/support/Makefile.inc<br />+ /minsoc/trunk/sw/support/mc.h<br />+ /minsoc/trunk/sw/support/orp.cfg<br />+ /minsoc/trunk/sw/support/orp.ld<br />+ /minsoc/trunk/sw/support/reset.S<br />+ /minsoc/trunk/sw/support/spr_defs.h<br />+ /minsoc/trunk/sw/support/support.c<br />+ /minsoc/trunk/sw/support/support.h<br />+ /minsoc/trunk/sw/support/uart.c<br />+ /minsoc/trunk/sw/support/uart.h<br />+ /minsoc/trunk/sw/support/vfnprintf.c<br />+ /minsoc/trunk/sw/support/vfnprintf.h<br />+ /minsoc/trunk/sw/uart<br />+ /minsoc/trunk/sw/uart/Makefile<br />+ /minsoc/trunk/sw/uart/uart.c<br />+ /minsoc/trunk/sw/uart/uart.h<br />+ /minsoc/trunk/sw/utils<br />+ /minsoc/trunk/sw/utils/bin2c.c<br />+ /minsoc/trunk/sw/utils/bin2flimg.c<br />+ /minsoc/trunk/sw/utils/bin2hex.c<br />+ /minsoc/trunk/sw/utils/bin2srec.c<br />+ /minsoc/trunk/sw/utils/bin2vmem.c<br />+ /minsoc/trunk/sw/utils/loader.c<br />+ /minsoc/trunk/sw/utils/Makefile<br />+ /minsoc/trunk/sw/utils/marksec<br />+ /minsoc/trunk/sw/utils/merge2srec<br />+ /minsoc/trunk/sw/utils/or32-idecode<br />+ /minsoc/trunk/sw/utils/or32-idecode/ansidecl.h<br />+ /minsoc/trunk/sw/utils/or32-idecode/bfd.h<br />+ /minsoc/trunk/sw/utils/or32-idecode/dis-asm.h<br />+ /minsoc/trunk/sw/utils/or32-idecode/example_input<br />+ /minsoc/trunk/sw/utils/or32-idecode/Makefile<br />+ /minsoc/trunk/sw/utils/or32-idecode/or32-dis.c<br />+ /minsoc/trunk/sw/utils/or32-idecode/or32-opc.c<br />+ /minsoc/trunk/sw/utils/or32-idecode/or32.h<br />+ /minsoc/trunk/sw/utils/or32-idecode/symcat.h<br /> rfajardo Fri, 18 Sep 2009 11:46:11 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Frtl%2Fverilog%2F&rev=2
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