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https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-0.9%2Fsw%2F&
Thu, 28 Mar 2024 15:21:37 +0100
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Tagging release 0.9 of MinSoC.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-0.9%2Fsw%2F&rev=42
<div><strong>Rev 42 - rfajardo</strong> (1 file(s) modified)</div><div>Tagging release 0.9 of MinSoC.</div>+ /minsoc/tags/release-0.9<br />
rfajardo
Tue, 15 Mar 2011 14:28:35 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-0.9%2Fsw%2F&rev=42
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FAQ:
-Adv_jtag_bridge self test fails?
...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsw%2F&rev=39
<div><strong>Rev 39 - rfajardo</strong> (4 file(s) modified)</div><div>FAQ:<br />
-Adv_jtag_bridge self test fails? <br />
...</div>~ /minsoc/trunk/doc/FAQ.pdf<br />~ /minsoc/trunk/doc/src/FAQ.odt<br />- /minsoc/trunk/sw/eth/eth.h<br />- /minsoc/trunk/sw/uart/uart.h<br />
rfajardo
Mon, 03 Jan 2011 22:57:12 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsw%2F&rev=39
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Small update to HOWTO: advices now to also include the ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsw%2F&rev=38
<div><strong>Rev 38 - rfajardo</strong> (5 file(s) modified)</div><div>Small update to HOWTO: advices now to also include the ...</div>~ /minsoc/trunk/doc/FAQ.pdf<br />~ /minsoc/trunk/doc/HOWTO.pdf<br />~ /minsoc/trunk/doc/src/FAQ.odt<br />~ /minsoc/trunk/doc/src/HOWTO.odt<br />~ /minsoc/trunk/sw/uart/uart.c<br />
rfajardo
Mon, 29 Nov 2010 23:39:21 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsw%2F&rev=38
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README.txt added, describing the installation and set-up processes. Also describing ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsw%2F&rev=37
<div><strong>Rev 37 - rfajardo</strong> (13 file(s) modified)</div><div>README.txt added, describing the installation and set-up processes. Also describing ...</div>~ /minsoc/trunk/doc/FAQ.pdf<br />~ /minsoc/trunk/doc/minsoc.pdf<br />+ /minsoc/trunk/doc/README.txt<br />~ /minsoc/trunk/doc/src/FAQ.odt<br />~ /minsoc/trunk/doc/src/minsoc.odt<br />~ /minsoc/trunk/doc/src/synthesis_examples.odt<br />~ /minsoc/trunk/doc/synthesis_examples.pdf<br />~ /minsoc/trunk/sw/drivers/eth.c<br />- /minsoc/trunk/sw/utils/loader.c<br />~ /minsoc/trunk/sw/utils/Makefile<br />- /minsoc/trunk/sw/utils/marksec<br />- /minsoc/trunk/sw/utils/merge2srec<br />- /minsoc/trunk/sw/utils/or32-idecode<br />
rfajardo
Sat, 30 Oct 2010 12:40:04 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsw%2F&rev=37
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utils: -adding a 32 to 8 bit Wishbone bridge to ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsw%2F&rev=36
<div><strong>Rev 36 - rfajardo</strong> (35 file(s) modified)</div><div>utils: -adding a 32 to 8 bit Wishbone bridge to ...</div>~ /minsoc/trunk/doc/FAQ.pdf<br />~ /minsoc/trunk/doc/HOWTO.pdf<br />~ /minsoc/trunk/doc/INSTALL.pdf<br />~ /minsoc/trunk/doc/src/FAQ.odt<br />~ /minsoc/trunk/doc/src/HOWTO.odt<br />~ /minsoc/trunk/doc/src/INSTALL.odt<br />+ /minsoc/trunk/sw/drivers<br />+ /minsoc/trunk/sw/drivers/can.c<br />+ /minsoc/trunk/sw/drivers/can.h<br />+ /minsoc/trunk/sw/drivers/eth.c<br />+ /minsoc/trunk/sw/drivers/eth.h<br />+ /minsoc/trunk/sw/drivers/i2c.c<br />+ /minsoc/trunk/sw/drivers/i2c.h<br />+ /minsoc/trunk/sw/drivers/interrupts.c<br />+ /minsoc/trunk/sw/drivers/Makefile<br />+ /minsoc/trunk/sw/drivers/tick.c<br />+ /minsoc/trunk/sw/drivers/tick.h<br />+ /minsoc/trunk/sw/drivers/uart.c<br />+ /minsoc/trunk/sw/drivers/uart.h<br />~ /minsoc/trunk/sw/eth/eth.c<br />~ /minsoc/trunk/sw/eth/eth.h<br />~ /minsoc/trunk/sw/eth/Makefile<br />~ /minsoc/trunk/sw/support/board.h<br />~ /minsoc/trunk/sw/support/except.S<br />~ /minsoc/trunk/sw/support/Makefile<br />~ /minsoc/trunk/sw/support/Makefile.inc<br />~ /minsoc/trunk/sw/support/support.c<br />~ /minsoc/trunk/sw/support/support.h<br />~ /minsoc/trunk/sw/support/uart.c<br />~ /minsoc/trunk/sw/support/vfnprintf.c<br />~ /minsoc/trunk/sw/uart/Makefile<br />~ /minsoc/trunk/sw/uart/uart.c<br />+ /minsoc/trunk/utils<br />+ /minsoc/trunk/utils/cable_parallel.c<br />+ /minsoc/trunk/utils/minsoc_wb_32_8_bridge.v<br />
rfajardo
Fri, 29 Oct 2010 17:05:31 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsw%2F&rev=36
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External interrupt processing was being run multiple times because:
...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsw%2F&rev=11
<div><strong>Rev 11 - rfajardo</strong> (2 file(s) modified)</div><div>External interrupt processing was being run multiple times because:<br />
...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/sw/support/int.c<br />
rfajardo
Fri, 23 Oct 2009 14:49:17 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsw%2F&rev=11
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First commit of project. Beta status:
-testbench: ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsw%2F&rev=2
<div><strong>Rev 2 - rfajardo</strong> (92 file(s) modified)</div><div>First commit of project. Beta status:<br />
-testbench: ...</div>+ /minsoc/trunk/backend<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit.ucf<br />+ /minsoc/trunk/backend/spartan3e_starter_kit.ucf<br />+ /minsoc/trunk/bench<br />+ /minsoc/trunk/bench/verilog<br />+ /minsoc/trunk/bench/verilog/eth_phy.v<br />+ /minsoc/trunk/bench/verilog/eth_phy_defines.v<br />+ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />+ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />+ /minsoc/trunk/bench/verilog/minsoc_memory_model.v<br />+ /minsoc/trunk/bench/verilog/tb_eth_defines.v<br />+ /minsoc/trunk/bench/verilog/vpi<br />+ /minsoc/trunk/bench/verilog/vpi/dbg_comm_vpi.v<br />+ /minsoc/trunk/bench/verilog/vpi/jp-io-vpi.vpi<br />+ /minsoc/trunk/doc<br />+ /minsoc/trunk/doc/lgpl-3.0.txt<br />+ /minsoc/trunk/doc/minsoc.odt<br />+ /minsoc/trunk/doc/minsoc.pdf<br />+ /minsoc/trunk/rtl<br />+ /minsoc/trunk/rtl/verilog<br />+ /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_onchip_ram.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_onchip_ram_top.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/OR1K_startup_generic.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_clgen.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_defines.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_shift.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_top.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_tc_top.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_xilinx_internal_jtag.v<br />+ /minsoc/trunk/sim<br />+ /minsoc/trunk/sim/bin<br />+ /minsoc/trunk/sim/bin/minsoc_memory_complete.txt<br />+ /minsoc/trunk/sim/bin/minsoc_memory_fast.txt<br />+ /minsoc/trunk/sim/bin/minsoc_model_complete.txt<br />+ /minsoc/trunk/sim/bin/minsoc_model_fast.txt<br />+ /minsoc/trunk/sim/results<br />+ /minsoc/trunk/sim/results/wave.do.sav<br />+ /minsoc/trunk/sim/run<br />+ /minsoc/trunk/sim/run/generate_bench<br />+ /minsoc/trunk/sim/run/run_bench<br />+ /minsoc/trunk/sim/run/start_server<br />+ /minsoc/trunk/sw<br />+ /minsoc/trunk/sw/eth<br />+ /minsoc/trunk/sw/eth/eth.c<br />+ /minsoc/trunk/sw/eth/eth.h<br />+ /minsoc/trunk/sw/eth/Makefile<br />+ /minsoc/trunk/sw/support<br />+ /minsoc/trunk/sw/support/board.h<br />+ /minsoc/trunk/sw/support/except.S<br />+ /minsoc/trunk/sw/support/int.c<br />+ /minsoc/trunk/sw/support/int.h<br />+ /minsoc/trunk/sw/support/Makefile<br />+ /minsoc/trunk/sw/support/Makefile.inc<br />+ /minsoc/trunk/sw/support/mc.h<br />+ /minsoc/trunk/sw/support/orp.cfg<br />+ /minsoc/trunk/sw/support/orp.ld<br />+ /minsoc/trunk/sw/support/reset.S<br />+ /minsoc/trunk/sw/support/spr_defs.h<br />+ /minsoc/trunk/sw/support/support.c<br />+ /minsoc/trunk/sw/support/support.h<br />+ /minsoc/trunk/sw/support/uart.c<br />+ /minsoc/trunk/sw/support/uart.h<br />+ /minsoc/trunk/sw/support/vfnprintf.c<br />+ /minsoc/trunk/sw/support/vfnprintf.h<br />+ /minsoc/trunk/sw/uart<br />+ /minsoc/trunk/sw/uart/Makefile<br />+ /minsoc/trunk/sw/uart/uart.c<br />+ /minsoc/trunk/sw/uart/uart.h<br />+ /minsoc/trunk/sw/utils<br />+ /minsoc/trunk/sw/utils/bin2c.c<br />+ /minsoc/trunk/sw/utils/bin2flimg.c<br />+ /minsoc/trunk/sw/utils/bin2hex.c<br />+ /minsoc/trunk/sw/utils/bin2srec.c<br />+ /minsoc/trunk/sw/utils/bin2vmem.c<br />+ /minsoc/trunk/sw/utils/loader.c<br />+ /minsoc/trunk/sw/utils/Makefile<br />+ /minsoc/trunk/sw/utils/marksec<br />+ /minsoc/trunk/sw/utils/merge2srec<br />+ /minsoc/trunk/sw/utils/or32-idecode<br />+ /minsoc/trunk/sw/utils/or32-idecode/ansidecl.h<br />+ /minsoc/trunk/sw/utils/or32-idecode/bfd.h<br />+ /minsoc/trunk/sw/utils/or32-idecode/dis-asm.h<br />+ /minsoc/trunk/sw/utils/or32-idecode/example_input<br />+ /minsoc/trunk/sw/utils/or32-idecode/Makefile<br />+ /minsoc/trunk/sw/utils/or32-idecode/or32-dis.c<br />+ /minsoc/trunk/sw/utils/or32-idecode/or32-opc.c<br />+ /minsoc/trunk/sw/utils/or32-idecode/or32.h<br />+ /minsoc/trunk/sw/utils/or32-idecode/symcat.h<br />
rfajardo
Fri, 18 Sep 2009 11:46:11 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsw%2F&rev=2
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