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minsoc WebSVN RSS feed - minsoc https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-1.0%2Fbackend%2F& Wed, 21 Oct 2020 11:12:16 +0100 FeedCreator 1.7.2 Creating tag release-1.0 from revision 150 of branches/rc-1.0. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-1.0%2Fbackend%2F&rev=151 <div><strong>Rev 151 - rfajardo</strong> (1 file(s) modified)</div><div>Creating tag release-1.0 from revision 150 of branches/rc-1.0.</div>+ /minsoc/tags/release-1.0<br /> rfajardo Mon, 28 Nov 2011 10:44:14 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-1.0%2Fbackend%2F&rev=151 Updating minsoc_bench.v to correctly acquire uart data. Uart drivers: when ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=147 <div><strong>Rev 147 - rfajardo</strong> (11 file(s) modified)</div><div>Updating minsoc_bench.v to correctly acquire uart data. <br /> <br /> Uart drivers: when ...</div>~ /minsoc/branches/rc-1.0/backend/altera_3c25_board/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/std/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/ug257/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />~ /minsoc/branches/rc-1.0/sim/run/run_bench<br />~ /minsoc/branches/rc-1.0/sw/drivers/uart.c<br />~ /minsoc/branches/rc-1.0/sw/eth/eth.c<br />~ /minsoc/branches/rc-1.0/sw/uart/uart.c<br />~ /minsoc/branches/rc-1.0/utils/setup/minsoc-install.sh<br /> rfajardo Wed, 23 Nov 2011 12:29:02 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=147 Importing 'Xilinx Microblaze Dev. Kit 1600E Edition' board configuration directory. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=146 <div><strong>Rev 146 - ConX.</strong> (9 file(s) modified)</div><div>Importing 'Xilinx Microblaze Dev. Kit 1600E Edition' board configuration directory.</div>+ /minsoc/branches/rc-1.0/backend/ug257<br />+ /minsoc/branches/rc-1.0/backend/ug257/board.h<br />+ /minsoc/branches/rc-1.0/backend/ug257/configure<br />+ /minsoc/branches/rc-1.0/backend/ug257/gcc-opt.mk<br />+ /minsoc/branches/rc-1.0/backend/ug257/minsoc_bench_defines.v<br />+ /minsoc/branches/rc-1.0/backend/ug257/minsoc_defines.v<br />+ /minsoc/branches/rc-1.0/backend/ug257/or1200_defines.v<br />+ /minsoc/branches/rc-1.0/backend/ug257/orp.ld<br />+ /minsoc/branches/rc-1.0/backend/ug257/ug257.ucf<br /> ConX. Wed, 23 Nov 2011 06:33:07 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=146 Compiling firmwares in board configuration scripts instead of on global ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=143 <div><strong>Rev 143 - rfajardo</strong> (5 file(s) modified)</div><div>Compiling firmwares in board configuration scripts instead of on global ...</div>~ /minsoc/branches/rc-1.0/backend/altera_3c25_board/configure<br />~ /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/configure<br />~ /minsoc/branches/rc-1.0/backend/std/configure<br />~ /minsoc/branches/rc-1.0/utils/setup/configure.sh<br /> rfajardo Tue, 22 Nov 2011 10:59:03 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=143 Removing uncomplete support for ml509 and not working support for ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=137 <div><strong>Rev 137 - rfajardo</strong> (2 file(s) modified)</div><div>Removing uncomplete support for ml509 and not working support for ...</div>- /minsoc/branches/rc-1.0/backend/ml509<br />- /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit_eth<br /> rfajardo Mon, 21 Nov 2011 10:45:03 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=137 Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=124 <div><strong>Rev 124 - rfajardo</strong> (6 file(s) modified)</div><div>Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart ...</div>~ /minsoc/branches/rc-1.0/backend/altera_3c25_board/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/std/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br /> rfajardo Wed, 02 Nov 2011 15:27:24 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=124 Configure scripts for Xilinx devices updated. All of them require ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=118 <div><strong>Rev 118 - rfajardo</strong> (4 file(s) modified)</div><div>Configure scripts for Xilinx devices updated. All of them require ...</div>~ /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/configure<br />+ /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/or1200_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/configure<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit_eth/configure<br /> rfajardo Thu, 27 Oct 2011 16:16:18 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=118 spartan3e_starter_kit designs require DUALPORT from or1200_defines.v to be active instead ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=117 <div><strong>Rev 117 - rfajardo</strong> (2 file(s) modified)</div><div>spartan3e_starter_kit designs require DUALPORT from or1200_defines.v to be active instead ...</div>~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/or1200_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit_eth/or1200_defines.v<br /> rfajardo Thu, 27 Oct 2011 15:27:12 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=117 Configure scripts were trying to copy/patch projects files before creating ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=116 <div><strong>Rev 116 - rfajardo</strong> (5 file(s) modified)</div><div>Configure scripts were trying to copy/patch projects files before creating ...</div>~ /minsoc/branches/rc-1.0/backend/altera_3c25_board/configure<br />~ /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/configure<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/branches/rc-1.0/backend/std/configure<br /> rfajardo Thu, 27 Oct 2011 14:53:51 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=116 minsoc-install.sh &amp; minsoc-configure.sh: -aware of location ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=113 <div><strong>Rev 113 - rfajardo</strong> (7 file(s) modified)</div><div>minsoc-install.sh &amp; minsoc-configure.sh: <br /> -aware of location ...</div>~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/or1200_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit_eth/or1200_defines.v<br />~ /minsoc/branches/rc-1.0/prj/Makefile<br />~ /minsoc/branches/rc-1.0/prj/src/blackboxes/or1200_top.v<br />~ /minsoc/branches/rc-1.0/utils/setup/configure.sh<br />~ /minsoc/branches/rc-1.0/utils/setup/minsoc-configure.sh<br />~ /minsoc/branches/rc-1.0/utils/setup/minsoc-install.sh<br /> rfajardo Thu, 27 Oct 2011 13:49:07 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=113 Fixing several minor issues with the system: ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=110 <div><strong>Rev 110 - rfajardo</strong> (13 file(s) modified)</div><div>Fixing several minor issues with the system:<br /> ...</div>~ /minsoc/branches/rc-1.0/backend/altera_3c25_board/configure<br />~ /minsoc/branches/rc-1.0/prj/Makefile<br />- /minsoc/branches/rc-1.0/prj/scripts/altprj.sh<br />+ /minsoc/branches/rc-1.0/prj/scripts/altvhdprj.sh<br />+ /minsoc/branches/rc-1.0/prj/scripts/altvprj.sh<br />~ /minsoc/branches/rc-1.0/prj/scripts/simverilog.sh<br />~ /minsoc/branches/rc-1.0/prj/scripts/simvhdl.sh<br />~ /minsoc/branches/rc-1.0/prj/scripts/xilinxprj.sh<br />~ /minsoc/branches/rc-1.0/prj/src/or1200_top.prj<br />~ /minsoc/branches/rc-1.0/rtl/verilog<br />+ /minsoc/branches/rc-1.0/utils/setup/configure.sh<br />+ /minsoc/branches/rc-1.0/utils/setup/minsoc-configure.sh<br />~ /minsoc/branches/rc-1.0/utils/setup/minsoc-install.sh<br /> rfajardo Wed, 26 Oct 2011 21:41:05 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=110 Creating a branche for release candidate 1.0. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=109 <div><strong>Rev 109 - rfajardo</strong> (1 file(s) modified)</div><div>Creating a branche for release candidate 1.0.</div>+ /minsoc/branches/rc-1.0<br /> rfajardo Wed, 26 Oct 2011 19:51:48 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Frc-1.0%2Fbackend%2F&rev=109 Updating configure scripts to copy Windows synthesis launch script setup.bat ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2F&rev=105 <div><strong>Rev 105 - rfajardo</strong> (7 file(s) modified)</div><div>Updating configure scripts to copy Windows synthesis launch script setup.bat ...</div>~ /minsoc/trunk/backend/altera_3c25_board/configure<br />~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/trunk/backend/std/configure<br />- /minsoc/trunk/syn/setup.bat<br />+ /minsoc/trunk/syn/xilinx/setup.bat<br /> rfajardo Wed, 26 Oct 2011 09:09:30 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2F&rev=105 backend/altera_3c25_board/minsoc_defines. ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2F&rev=99 <div><strong>Rev 99 - rfajardo</strong> (1 file(s) modified)</div><div>backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid ...</div>~ /minsoc/trunk/backend/altera_3c25_board/minsoc_defines.v<br /> rfajardo Mon, 12 Sep 2011 09:30:45 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2F&rev=99 As proposed by Javier Almansa automatically generated project files for ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2F&rev=97 <div><strong>Rev 97 - rfajardo</strong> (32 file(s) modified)</div><div>As proposed by Javier Almansa automatically generated project files for ...</div>~ /minsoc/trunk/backend/altera_3c25_board/configure<br />~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/trunk/backend/std/configure<br />- /minsoc/trunk/prj/altera/adbg_top.prj<br />- /minsoc/trunk/prj/altera/altera_virtual_jtag.prj<br />- /minsoc/trunk/prj/altera/ethmac.prj<br />- /minsoc/trunk/prj/altera/jtag_top.prj<br />- /minsoc/trunk/prj/altera/minsoc_bench.prj<br />- /minsoc/trunk/prj/altera/minsoc_top.prj<br />- /minsoc/trunk/prj/altera/or1200_top.prj<br />- /minsoc/trunk/prj/altera/uart_top.prj<br />- /minsoc/trunk/prj/sim/adbg_top.src<br />- /minsoc/trunk/prj/sim/ethmac.src<br />- /minsoc/trunk/prj/sim/jtag_top.src<br />- /minsoc/trunk/prj/sim/minsoc.src<br />- /minsoc/trunk/prj/sim/minsoc_top.src<br />- /minsoc/trunk/prj/sim/or1200_top.src<br />- /minsoc/trunk/prj/sim/uart_top.src<br />- /minsoc/trunk/prj/xilinx/adbg_top.prj<br />- /minsoc/trunk/prj/xilinx/adbg_top.xst<br />- /minsoc/trunk/prj/xilinx/ethmac.prj<br />- /minsoc/trunk/prj/xilinx/ethmac.xst<br />- /minsoc/trunk/prj/xilinx/jtag_top.prj<br />- /minsoc/trunk/prj/xilinx/jtag_top.xst<br />- /minsoc/trunk/prj/xilinx/minsoc_top.prj<br />- /minsoc/trunk/prj/xilinx/minsoc_top.xst<br />- /minsoc/trunk/prj/xilinx/or1200_top.prj<br />- /minsoc/trunk/prj/xilinx/or1200_top.xst<br />- /minsoc/trunk/prj/xilinx/uart_top.prj<br />- /minsoc/trunk/prj/xilinx/uart_top.xst<br /> rfajardo Mon, 12 Sep 2011 08:54:47 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2F&rev=97 Some files needed for Altera synthesis https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2F&rev=96 <div><strong>Rev 96 - javieralso</strong> (5 file(s) modified)</div><div>Some files needed for Altera synthesis</div>~ /minsoc/trunk/backend/altera_3c25_board/configure<br />+ /minsoc/trunk/prj/altera/altera_virtual_jtag.prj<br />~ /minsoc/trunk/prj/Makefile<br />+ /minsoc/trunk/prj/scripts/altprj.sh<br />+ /minsoc/trunk/prj/src/altera_virtual_jtag.prj<br /> javieralso Sun, 11 Sep 2011 22:08:57 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2F&rev=96 Makefile for Altera FPGAs fixed https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2F&rev=95 <div><strong>Rev 95 - javieralso</strong> (17 file(s) modified)</div><div>Makefile for Altera FPGAs fixed</div>~ /minsoc/trunk/backend/altera_3c25_board/configure<br />~ /minsoc/trunk/backend/altera_3c25_board/minsoc_defines.v<br />+ /minsoc/trunk/prj/altera/adbg_top.prj<br />- /minsoc/trunk/prj/altera/adv_dbg.prj<br />- /minsoc/trunk/prj/altera/altera_jtag.prj<br />/minsoc/trunk/prj/altera/ethmac.prj<br />+ /minsoc/trunk/prj/altera/jtag_top.prj<br />+ /minsoc/trunk/prj/altera/minsoc_bench.prj<br />/minsoc/trunk/prj/altera/minsoc_top.prj<br />- /minsoc/trunk/prj/altera/minsoc_top.qsf<br />- /minsoc/trunk/prj/altera/or1k.prj<br />+ /minsoc/trunk/prj/altera/or1200_top.prj<br />- /minsoc/trunk/prj/altera/uart16550.prj<br />+ /minsoc/trunk/prj/altera/uart_top.prj<br />~ /minsoc/trunk/prj/Makefile<br />~ /minsoc/trunk/syn/altera/Makefile<br />+ /minsoc/trunk/syn/altera/minsoc_top.qsf<br /> javieralso Sat, 10 Sep 2011 19:03:56 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2F&rev=95 Support for Altera synthesis. It needs some tune, but it ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2F&rev=93 <div><strong>Rev 93 - javieralso</strong> (17 file(s) modified)</div><div>Support for Altera synthesis. It needs some tune, but it ...</div>+ /minsoc/trunk/backend/altera_3c25_board<br />+ /minsoc/trunk/backend/altera_3c25_board/altera_3c25_board.ucf<br />+ /minsoc/trunk/backend/altera_3c25_board/board.h<br />+ /minsoc/trunk/backend/altera_3c25_board/configure<br />+ /minsoc/trunk/backend/altera_3c25_board/gcc-opt.mk<br />+ /minsoc/trunk/backend/altera_3c25_board/minsoc_bench_defines.v<br />+ /minsoc/trunk/backend/altera_3c25_board/minsoc_defines.v<br />+ /minsoc/trunk/backend/altera_3c25_board/orp.ld<br />+ /minsoc/trunk/prj/altera/adv_dbg.prj<br />+ /minsoc/trunk/prj/altera/altera_jtag.prj<br />+ /minsoc/trunk/prj/altera/ethmac.prj<br />+ /minsoc/trunk/prj/altera/minsoc_top.prj<br />+ /minsoc/trunk/prj/altera/minsoc_top.qsf<br />+ /minsoc/trunk/prj/altera/or1k.prj<br />+ /minsoc/trunk/prj/altera/uart16550.prj<br />+ /minsoc/trunk/syn/altera<br />+ /minsoc/trunk/syn/altera/Makefile<br /> javieralso Thu, 08 Sep 2011 07:33:25 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2F&rev=93 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2F&rev=92 <div><strong>Rev 92 - rfajardo</strong> (2 file(s) modified)</div><div>backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it ...</div>~ /minsoc/trunk/backend/spartan3e_starter_kit/or1200_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/or1200_defines.v<br /> rfajardo Wed, 07 Sep 2011 09:37:23 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2F&rev=92 Project structure, Xilinx Makefiles and simulation working. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2F&rev=88 <div><strong>Rev 88 - rfajardo</strong> (20 file(s) modified)</div><div>Project structure, Xilinx Makefiles and simulation working.</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_defines.v<br />~ /minsoc/trunk/prj/Makefile<br />~ /minsoc/trunk/prj/scripts/simprj.sh<br />~ /minsoc/trunk/prj/scripts/xilinxprj.sh<br />~ /minsoc/trunk/prj/scripts/xilinxxst.sh<br />~ /minsoc/trunk/prj/sim/minsoc.src<br />~ /minsoc/trunk/prj/sim/minsoc_top.src<br />+ /minsoc/trunk/prj/src/minsoc_bench.prj<br />~ /minsoc/trunk/prj/src/minsoc_top.prj<br />~ /minsoc/trunk/prj/xilinx/adbg_top.xst<br />~ /minsoc/trunk/prj/xilinx/ethmac.xst<br />~ /minsoc/trunk/prj/xilinx/jtag_top.xst<br />~ /minsoc/trunk/prj/xilinx/minsoc_top.prj<br />~ /minsoc/trunk/prj/xilinx/minsoc_top.xst<br />~ /minsoc/trunk/prj/xilinx/or1200_top.xst<br />~ /minsoc/trunk/prj/xilinx/uart_top.xst<br />~ /minsoc/trunk/rtl/verilog/xilinx_dcm.v<br />~ /minsoc/trunk/syn/xilinx/Makefile<br /> rfajardo Tue, 06 Sep 2011 16:54:44 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2F&rev=88
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