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https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-1.0%2Fbench%2Fverilog%2Fminsoc_bench.v&
Fri, 29 Mar 2024 06:37:41 +0100
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Creating tag release-1.0 from revision 150 of branches/rc-1.0.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-1.0%2Fbench%2Fverilog%2F&rev=151
<div><strong>Rev 151 - rfajardo</strong> (1 file(s) modified)</div><div>Creating tag release-1.0 from revision 150 of branches/rc-1.0.</div>+ /minsoc/tags/release-1.0<br />
rfajardo
Mon, 28 Nov 2011 10:44:14 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-1.0%2Fbench%2Fverilog%2F&rev=151
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Renaming minsoc_wave.lxt to minsoc_wave.lxt2 for correctness.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-1.0%2Fbench%2Fverilog%2F&rev=148
<div><strong>Rev 148 - rfajardo</strong> (1 file(s) modified)</div><div>Renaming minsoc_wave.lxt to minsoc_wave.lxt2 for correctness.</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />
rfajardo
Wed, 23 Nov 2011 13:56:35 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-1.0%2Fbench%2Fverilog%2F&rev=148
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Updating minsoc_bench.v to correctly acquire uart data.
Uart drivers: when ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-1.0%2Fbench%2Fverilog%2F&rev=147
<div><strong>Rev 147 - rfajardo</strong> (11 file(s) modified)</div><div>Updating minsoc_bench.v to correctly acquire uart data. <br />
<br />
Uart drivers: when ...</div>~ /minsoc/branches/rc-1.0/backend/altera_3c25_board/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/std/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/backend/ug257/minsoc_bench_defines.v<br />~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />~ /minsoc/branches/rc-1.0/sim/run/run_bench<br />~ /minsoc/branches/rc-1.0/sw/drivers/uart.c<br />~ /minsoc/branches/rc-1.0/sw/eth/eth.c<br />~ /minsoc/branches/rc-1.0/sw/uart/uart.c<br />~ /minsoc/branches/rc-1.0/utils/setup/minsoc-install.sh<br />
rfajardo
Wed, 23 Nov 2011 12:29:02 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-1.0%2Fbench%2Fverilog%2F&rev=147
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Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-1.0%2Fbench%2Fverilog%2F&rev=133
<div><strong>Rev 133 - rfajardo</strong> (7 file(s) modified)</div><div>Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock ...</div>+ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_core.v<br />~ /minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj<br />~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.bat<br />~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.sh<br />~ /minsoc/branches/rc-1.0/sim/run/run_bench<br />~ /minsoc/branches/rc-1.0/sw/utils/bin2hex.c<br />
rfajardo
Mon, 07 Nov 2011 09:48:11 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-1.0%2Fbench%2Fverilog%2F&rev=133
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