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minsoc WebSVN RSS feed - minsoc https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-1.0%2Frtl%2Fverilog%2Ftimescale.v& Thu, 28 Mar 2024 23:34:37 +0100 FeedCreator 1.7.2 Creating tag release-1.0 from revision 150 of branches/rc-1.0. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-1.0%2Frtl%2Fverilog%2F&rev=151 <div><strong>Rev 151 - rfajardo</strong> (1 file(s) modified)</div><div>Creating tag release-1.0 from revision 150 of branches/rc-1.0.</div>+ /minsoc/tags/release-1.0<br /> rfajardo Mon, 28 Nov 2011 10:44:14 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-1.0%2Frtl%2Fverilog%2F&rev=151 Creating a branche for release candidate 1.0. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-1.0%2Frtl%2Fverilog%2F&rev=109 <div><strong>Rev 109 - rfajardo</strong> (1 file(s) modified)</div><div>Creating a branche for release candidate 1.0.</div>+ /minsoc/branches/rc-1.0<br /> rfajardo Wed, 26 Oct 2011 19:51:48 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-1.0%2Frtl%2Fverilog%2F&rev=109 Including a global timescale under minsoc/rtl/verilog to control simulation. It ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-1.0%2Frtl%2Fverilog%2F&rev=70 <div><strong>Rev 70 - rfajardo</strong> (10 file(s) modified)</div><div>Including a global timescale under minsoc/rtl/verilog to control simulation. It ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/std/minsoc_bench_defines.v<br />+ /minsoc/trunk/rtl/verilog/timescale.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />+ /minsoc/trunk/sim/modelsim<br />+ /minsoc/trunk/sim/modelsim/compile_design.sh<br />+ /minsoc/trunk/sim/modelsim/prepare_modelsim.sh<br />+ /minsoc/trunk/sim/modelsim/run_sim.sh<br /> rfajardo Tue, 10 May 2011 10:06:07 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftags%2Frelease-1.0%2Frtl%2Fverilog%2F&rev=70
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