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https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2Fspartan3e_starter_kit_eth%2F&
Thu, 28 Mar 2024 15:51:20 +0100
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As proposed by Javier Almansa automatically generated project files for ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2Fspartan3e_starter_kit_eth%2F&rev=97
<div><strong>Rev 97 - rfajardo</strong> (32 file(s) modified)</div><div>As proposed by Javier Almansa automatically generated project files for ...</div>~ /minsoc/trunk/backend/altera_3c25_board/configure<br />~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/trunk/backend/std/configure<br />- /minsoc/trunk/prj/altera/adbg_top.prj<br />- /minsoc/trunk/prj/altera/altera_virtual_jtag.prj<br />- /minsoc/trunk/prj/altera/ethmac.prj<br />- /minsoc/trunk/prj/altera/jtag_top.prj<br />- /minsoc/trunk/prj/altera/minsoc_bench.prj<br />- /minsoc/trunk/prj/altera/minsoc_top.prj<br />- /minsoc/trunk/prj/altera/or1200_top.prj<br />- /minsoc/trunk/prj/altera/uart_top.prj<br />- /minsoc/trunk/prj/sim/adbg_top.src<br />- /minsoc/trunk/prj/sim/ethmac.src<br />- /minsoc/trunk/prj/sim/jtag_top.src<br />- /minsoc/trunk/prj/sim/minsoc.src<br />- /minsoc/trunk/prj/sim/minsoc_top.src<br />- /minsoc/trunk/prj/sim/or1200_top.src<br />- /minsoc/trunk/prj/sim/uart_top.src<br />- /minsoc/trunk/prj/xilinx/adbg_top.prj<br />- /minsoc/trunk/prj/xilinx/adbg_top.xst<br />- /minsoc/trunk/prj/xilinx/ethmac.prj<br />- /minsoc/trunk/prj/xilinx/ethmac.xst<br />- /minsoc/trunk/prj/xilinx/jtag_top.prj<br />- /minsoc/trunk/prj/xilinx/jtag_top.xst<br />- /minsoc/trunk/prj/xilinx/minsoc_top.prj<br />- /minsoc/trunk/prj/xilinx/minsoc_top.xst<br />- /minsoc/trunk/prj/xilinx/or1200_top.prj<br />- /minsoc/trunk/prj/xilinx/or1200_top.xst<br />- /minsoc/trunk/prj/xilinx/uart_top.prj<br />- /minsoc/trunk/prj/xilinx/uart_top.xst<br />
rfajardo
Mon, 12 Sep 2011 08:54:47 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2Fspartan3e_starter_kit_eth%2F&rev=97
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backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2Fspartan3e_starter_kit_eth%2F&rev=92
<div><strong>Rev 92 - rfajardo</strong> (2 file(s) modified)</div><div>backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it ...</div>~ /minsoc/trunk/backend/spartan3e_starter_kit/or1200_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/or1200_defines.v<br />
rfajardo
Wed, 07 Sep 2011 09:37:23 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2Fspartan3e_starter_kit_eth%2F&rev=92
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Project structure, Xilinx Makefiles and simulation working.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2Fspartan3e_starter_kit_eth%2F&rev=88
<div><strong>Rev 88 - rfajardo</strong> (20 file(s) modified)</div><div>Project structure, Xilinx Makefiles and simulation working.</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_defines.v<br />~ /minsoc/trunk/prj/Makefile<br />~ /minsoc/trunk/prj/scripts/simprj.sh<br />~ /minsoc/trunk/prj/scripts/xilinxprj.sh<br />~ /minsoc/trunk/prj/scripts/xilinxxst.sh<br />~ /minsoc/trunk/prj/sim/minsoc.src<br />~ /minsoc/trunk/prj/sim/minsoc_top.src<br />+ /minsoc/trunk/prj/src/minsoc_bench.prj<br />~ /minsoc/trunk/prj/src/minsoc_top.prj<br />~ /minsoc/trunk/prj/xilinx/adbg_top.xst<br />~ /minsoc/trunk/prj/xilinx/ethmac.xst<br />~ /minsoc/trunk/prj/xilinx/jtag_top.xst<br />~ /minsoc/trunk/prj/xilinx/minsoc_top.prj<br />~ /minsoc/trunk/prj/xilinx/minsoc_top.xst<br />~ /minsoc/trunk/prj/xilinx/or1200_top.xst<br />~ /minsoc/trunk/prj/xilinx/uart_top.xst<br />~ /minsoc/trunk/rtl/verilog/xilinx_dcm.v<br />~ /minsoc/trunk/syn/xilinx/Makefile<br />
rfajardo
Tue, 06 Sep 2011 16:54:44 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2Fspartan3e_starter_kit_eth%2F&rev=88
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Synchronizing scripts to behave exactly the same.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2Fspartan3e_starter_kit_eth%2F&rev=87
<div><strong>Rev 87 - rfajardo</strong> (3 file(s) modified)</div><div>Synchronizing scripts to behave exactly the same.</div>~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/trunk/backend/std/configure<br />
rfajardo
Tue, 06 Sep 2011 15:47:46 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2Fspartan3e_starter_kit_eth%2F&rev=87
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Updating configure script messages.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2Fspartan3e_starter_kit_eth%2F&rev=86
<div><strong>Rev 86 - rfajardo</strong> (3 file(s) modified)</div><div>Updating configure script messages.</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />
rfajardo
Tue, 06 Sep 2011 15:41:45 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2Fspartan3e_starter_kit_eth%2F&rev=86
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Central project definition under prj. Synthesis and simulation take their ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2Fspartan3e_starter_kit_eth%2F&rev=85
<div><strong>Rev 85 - rfajardo</strong> (55 file(s) modified)</div><div>Central project definition under prj. Synthesis and simulation take their ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/trunk/backend/std/configure<br />+ /minsoc/trunk/prj<br />+ /minsoc/trunk/prj/altera<br />+ /minsoc/trunk/prj/Makefile<br />+ /minsoc/trunk/prj/scripts<br />+ /minsoc/trunk/prj/scripts/simprj.sh<br />+ /minsoc/trunk/prj/scripts/xilinxprj.sh<br />+ /minsoc/trunk/prj/scripts/xilinxxst.sh<br />+ /minsoc/trunk/prj/sim<br />+ /minsoc/trunk/prj/sim/adbg_top.src<br />+ /minsoc/trunk/prj/sim/ethmac.src<br />+ /minsoc/trunk/prj/sim/jtag_top.src<br />+ /minsoc/trunk/prj/sim/minsoc.src<br />+ /minsoc/trunk/prj/sim/minsoc_top.src<br />+ /minsoc/trunk/prj/sim/or1200_top.src<br />+ /minsoc/trunk/prj/sim/uart_top.src<br />+ /minsoc/trunk/prj/src<br />+ /minsoc/trunk/prj/src/adbg_top.prj<br />+ /minsoc/trunk/prj/src/blackboxes<br />+ /minsoc/trunk/prj/src/blackboxes/ethmac.v<br />- /minsoc/trunk/prj/src/blackboxes/eth_top.v<br />+ /minsoc/trunk/prj/src/ethmac.prj<br />+ /minsoc/trunk/prj/src/jtag_top.prj<br />+ /minsoc/trunk/prj/src/minsoc_top.prj<br />+ /minsoc/trunk/prj/src/or1200_top.prj<br />+ /minsoc/trunk/prj/src/uart_top.prj<br />+ /minsoc/trunk/prj/xilinx<br />+ /minsoc/trunk/prj/xilinx/adbg_top.prj<br />+ /minsoc/trunk/prj/xilinx/adbg_top.xst<br />+ /minsoc/trunk/prj/xilinx/ethmac.prj<br />+ /minsoc/trunk/prj/xilinx/ethmac.xst<br />+ /minsoc/trunk/prj/xilinx/jtag_top.prj<br />+ /minsoc/trunk/prj/xilinx/jtag_top.xst<br />+ /minsoc/trunk/prj/xilinx/minsoc_top.prj<br />+ /minsoc/trunk/prj/xilinx/minsoc_top.xst<br />+ /minsoc/trunk/prj/xilinx/or1200_top.prj<br />+ /minsoc/trunk/prj/xilinx/or1200_top.xst<br />+ /minsoc/trunk/prj/xilinx/uart_top.prj<br />+ /minsoc/trunk/prj/xilinx/uart_top.xst<br />- /minsoc/trunk/sim/bin<br />~ /minsoc/trunk/sim/modelsim/compile_design.bat<br />~ /minsoc/trunk/sim/modelsim/compile_design.sh<br />~ /minsoc/trunk/sim/run/generate_bench<br />- /minsoc/trunk/syn/blackboxes<br />- /minsoc/trunk/syn/buildSupport/adbg_top.prj<br />- /minsoc/trunk/syn/buildSupport/eth_top.prj<br />- /minsoc/trunk/syn/buildSupport/minsoc_top.prj<br />- /minsoc/trunk/syn/buildSupport/or1200_top.prj<br />- /minsoc/trunk/syn/buildSupport/uart_top.prj<br />- /minsoc/trunk/syn/src<br />+ /minsoc/trunk/syn/xilinx<br />+ /minsoc/trunk/syn/xilinx/Makefile<br />
rfajardo
Tue, 06 Sep 2011 15:34:18 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2Fspartan3e_starter_kit_eth%2F&rev=85
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Establishing a better Makefile system for firmwares.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2Fspartan3e_starter_kit_eth%2F&rev=80
<div><strong>Rev 80 - rfajardo</strong> (21 file(s) modified)</div><div>Establishing a better Makefile system for firmwares.</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/gcc-opt.mk<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/gcc-opt.mk<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/gcc-opt.mk<br />~ /minsoc/trunk/backend/std/gcc-opt.mk<br />~ /minsoc/trunk/sw/drivers/can.c<br />- /minsoc/trunk/sw/drivers/common.mk<br />~ /minsoc/trunk/sw/drivers/eth.c<br />~ /minsoc/trunk/sw/drivers/i2c.c<br />~ /minsoc/trunk/sw/drivers/Makefile<br />~ /minsoc/trunk/sw/drivers/uart.c<br />- /minsoc/trunk/sw/eth/common.mk<br />~ /minsoc/trunk/sw/eth/eth.c<br />~ /minsoc/trunk/sw/eth/Makefile<br />- /minsoc/trunk/sw/support/common.mk<br />~ /minsoc/trunk/sw/support/Makefile<br />~ /minsoc/trunk/sw/support/Makefile.inc<br />~ /minsoc/trunk/sw/support/reset.S<br />~ /minsoc/trunk/sw/support/support.c<br />- /minsoc/trunk/sw/uart/common.mk<br />~ /minsoc/trunk/sw/uart/Makefile<br />~ /minsoc/trunk/sw/uart/uart.c<br />
rfajardo
Fri, 19 Aug 2011 11:05:49 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2Fspartan3e_starter_kit_eth%2F&rev=80
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Including a global timescale under minsoc/rtl/verilog to control simulation. It ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2Fspartan3e_starter_kit_eth%2F&rev=70
<div><strong>Rev 70 - rfajardo</strong> (10 file(s) modified)</div><div>Including a global timescale under minsoc/rtl/verilog to control simulation. It ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/std/minsoc_bench_defines.v<br />+ /minsoc/trunk/rtl/verilog/timescale.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />+ /minsoc/trunk/sim/modelsim<br />+ /minsoc/trunk/sim/modelsim/compile_design.sh<br />+ /minsoc/trunk/sim/modelsim/prepare_modelsim.sh<br />+ /minsoc/trunk/sim/modelsim/run_sim.sh<br />
rfajardo
Tue, 10 May 2011 10:06:07 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2Fspartan3e_starter_kit_eth%2F&rev=70
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backend update:
-minsoc_bench_defines.v
...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2Fspartan3e_starter_kit_eth%2F&rev=69
<div><strong>Rev 69 - rfajardo</strong> (21 file(s) modified)</div><div>backend update: <br />
-minsoc_bench_defines.v<br />
...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/gcc-opt.mk<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/gcc-opt.mk<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/board.h<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/gcc-opt.mk<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/or1200_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/orp.ld<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/spartan3e_starter_kit_eth.ucf<br />~ /minsoc/trunk/backend/std/configure<br />+ /minsoc/trunk/backend/std/gcc-opt.mk<br />+ /minsoc/trunk/backend/std/minsoc_bench_defines.v<br />- /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />~ /minsoc/trunk/sw/support/Makefile.inc<br />
rfajardo
Thu, 05 May 2011 18:11:35 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbackend%2Fspartan3e_starter_kit_eth%2F&rev=69
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