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minsoc WebSVN RSS feed - minsoc https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F& Tue, 12 Nov 2019 21:48:24 +0100 FeedCreator 1.7.2 Tasks don't have parenthesis. This is only used for ports ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=162 <div><strong>Rev 162 - rfajardo</strong> (1 file(s) modified)</div><div>Tasks don't have parenthesis. This is only used for ports ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br /> rfajardo Fri, 20 Jan 2012 15:23:36 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=162 Decreased wait time, for faster simulations. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=155 <div><strong>Rev 155 - nyawn</strong> (1 file(s) modified)</div><div>Decreased wait time, for faster simulations.</div>~ /minsoc/trunk/bench/verilog/vpi/dbg_comm_vpi.v<br /> nyawn Sat, 31 Dec 2011 00:32:35 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=155 Merging differences of release candidate 1.0 revision 140:148 with trunk. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=149 <div><strong>Rev 149 - rfajardo</strong> (19 file(s) modified)</div><div>Merging differences of release candidate 1.0 revision 140:148 with trunk.</div>~ /minsoc/trunk<br />~ /minsoc/trunk/backend/altera_3c25_board/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/std/minsoc_bench_defines.v<br />+ /minsoc/trunk/backend/ug257<br />/minsoc/trunk/backend/ug257/board.h<br />/minsoc/trunk/backend/ug257/configure<br />/minsoc/trunk/backend/ug257/gcc-opt.mk<br />/minsoc/trunk/backend/ug257/minsoc_bench_defines.v<br />/minsoc/trunk/backend/ug257/minsoc_defines.v<br />/minsoc/trunk/backend/ug257/orp.ld<br />/minsoc/trunk/backend/ug257/ug257.ucf<br />~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/sim/run/run_bench<br />~ /minsoc/trunk/sw/drivers/uart.c<br />~ /minsoc/trunk/sw/eth/eth.c<br />~ /minsoc/trunk/sw/uart/uart.c<br />~ /minsoc/trunk/utils/setup/minsoc-install.sh<br /> rfajardo Mon, 28 Nov 2011 10:02:52 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=149 Merging with rc-1.0 revision 140. I doubt rc-1.0 will still ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=141 <div><strong>Rev 141 - rfajardo</strong> (32 file(s) modified)</div><div>Merging with rc-1.0 revision 140. I doubt rc-1.0 will still ...</div>~ /minsoc/trunk<br />~ /minsoc/trunk/backend/altera_3c25_board/configure<br />~ /minsoc/trunk/backend/altera_3c25_board/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/std/configure<br />~ /minsoc/trunk/backend/std/minsoc_bench_defines.v<br />/minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/prj/Makefile<br />- /minsoc/trunk/prj/scripts/altprj.sh<br />+ /minsoc/trunk/prj/scripts/altvhdprj.sh<br />+ /minsoc/trunk/prj/scripts/altvprj.sh<br />~ /minsoc/trunk/prj/scripts/simverilog.sh<br />~ /minsoc/trunk/prj/scripts/simvhdl.sh<br />~ /minsoc/trunk/prj/scripts/xilinxprj.sh<br />~ /minsoc/trunk/prj/src/ethmac.prj<br />~ /minsoc/trunk/sim/modelsim/compile_design.bat<br />~ /minsoc/trunk/sim/modelsim/prepare_modelsim.bat<br />~ /minsoc/trunk/sim/modelsim/run_sim.bat<br />~ /minsoc/trunk/sim/modelsim/run_sim.sh<br />~ /minsoc/trunk/sim/run/run_bench<br />~ /minsoc/trunk/sw/utils/bin2hex.c<br />~ /minsoc/trunk/syn/xilinx/setup.bat<br />~ /minsoc/trunk/utils/setup/beautify.sh<br />+ /minsoc/trunk/utils/setup/configure.sh<br />~ /minsoc/trunk/utils/setup/minsoc-install.sh<br />+ /minsoc/trunk/utils/setup/minsoc-setup.sh<br />~ /minsoc/trunk/utils/setup/required-cygwin-tools.txt<br /> rfajardo Tue, 22 Nov 2011 10:46:40 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=141 Modelsim whines about missing timescales: -minsoc_bench.v, minsoc_memory_model.v and ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=71 <div><strong>Rev 71 - rfajardo</strong> (3 file(s) modified)</div><div>Modelsim whines about missing timescales: <br /> -minsoc_bench.v, minsoc_memory_model.v and ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_memory_model.v<br />~ /minsoc/trunk/bench/verilog/vpi/dbg_comm_vpi.v<br /> rfajardo Tue, 10 May 2011 10:34:10 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=71 backend update: -minsoc_bench_defines.v ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=69 <div><strong>Rev 69 - rfajardo</strong> (21 file(s) modified)</div><div>backend update: <br /> -minsoc_bench_defines.v<br /> ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/gcc-opt.mk<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/gcc-opt.mk<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/board.h<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/gcc-opt.mk<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/or1200_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/orp.ld<br />+ /minsoc/trunk/backend/spartan3e_starter_kit_eth/spartan3e_starter_kit_eth.ucf<br />~ /minsoc/trunk/backend/std/configure<br />+ /minsoc/trunk/backend/std/gcc-opt.mk<br />+ /minsoc/trunk/backend/std/minsoc_bench_defines.v<br />- /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />~ /minsoc/trunk/sw/support/Makefile.inc<br /> rfajardo Thu, 05 May 2011 18:11:35 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=69 firmware makefiles: -every firmware makefile has now ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=64 <div><strong>Rev 64 - rfajardo</strong> (61 file(s) modified)</div><div>firmware makefiles:<br /> -every firmware makefile has now ...</div>+ /minsoc/trunk/backend/ml509<br />- /minsoc/trunk/backend/ml509.ucf<br />+ /minsoc/trunk/backend/ml509/ml509.ucf<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit<br />- /minsoc/trunk/backend/spartan3a_dsp_kit.ucf<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/board.h<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_defines.v<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/orp.ld<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf<br />+ /minsoc/trunk/backend/spartan3e_starter_kit<br />- /minsoc/trunk/backend/spartan3e_starter_kit.ucf<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/board.h<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/orp.ld<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf<br />+ /minsoc/trunk/backend/std<br />+ /minsoc/trunk/backend/std/board.h<br />+ /minsoc/trunk/backend/std/minsoc_defines.v<br />+ /minsoc/trunk/backend/std/orp.ld<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />- /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />~ /minsoc/trunk/sw/drivers/can.c<br />+ /minsoc/trunk/sw/drivers/common.mk<br />~ /minsoc/trunk/sw/drivers/eth.c<br />~ /minsoc/trunk/sw/drivers/i2c.c<br />- /minsoc/trunk/sw/drivers/Makefile<br />~ /minsoc/trunk/sw/drivers/uart.c<br />+ /minsoc/trunk/sw/eth/common.mk<br />~ /minsoc/trunk/sw/eth/eth.c<br />- /minsoc/trunk/sw/eth/Makefile<br />- /minsoc/trunk/sw/support/board.h<br />+ /minsoc/trunk/sw/support/common.mk<br />/minsoc/trunk/sw/support/Makefile<br />~ /minsoc/trunk/sw/support/Makefile.inc<br />- /minsoc/trunk/sw/support/orp.ld<br />~ /minsoc/trunk/sw/support/reset.S<br />~ /minsoc/trunk/sw/support/tick.c<br />+ /minsoc/trunk/sw/uart/common.mk<br />- /minsoc/trunk/sw/uart/Makefile<br />~ /minsoc/trunk/sw/uart/uart.c<br />- /minsoc/trunk/syn/blackboxes/OR1K_startup_generic.v<br />- /minsoc/trunk/syn/buildSupport/adbg_top.xst<br />- /minsoc/trunk/syn/buildSupport/eth_top.xst<br />- /minsoc/trunk/syn/buildSupport/minsoc_startup_top.prj<br />- /minsoc/trunk/syn/buildSupport/minsoc_startup_top.xst<br />~ /minsoc/trunk/syn/buildSupport/minsoc_top.prj<br />- /minsoc/trunk/syn/buildSupport/minsoc_top.xst<br />- /minsoc/trunk/syn/buildSupport/or1200_top.xst<br />- /minsoc/trunk/syn/buildSupport/uart_top.xst<br />- /minsoc/trunk/syn/Makefile<br />+ /minsoc/trunk/syn/src<br />+ /minsoc/trunk/syn/src/adbg_top.xst<br />+ /minsoc/trunk/syn/src/eth_top.xst<br />+ /minsoc/trunk/syn/src/Makefile<br />+ /minsoc/trunk/syn/src/minsoc_top.xst<br />+ /minsoc/trunk/syn/src/or1200_top.xst<br />+ /minsoc/trunk/syn/src/uart_top.xst<br />- /minsoc/trunk/utils/contributions/.directory<br /> rfajardo Tue, 03 May 2011 11:01:33 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=64 Selection of memory model or implementation memory is now made ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=60 <div><strong>Rev 60 - rfajardo</strong> (8 file(s) modified)</div><div>Selection of memory model or implementation memory is now made ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/bench/verilog/minsoc_memory_model.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />- /minsoc/trunk/sim/bin/minsoc_memory.txt<br />- /minsoc/trunk/sim/bin/minsoc_model.txt<br />+ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />~ /minsoc/trunk/sim/run/generate_bench<br /> rfajardo Thu, 28 Apr 2011 22:44:09 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=60 undefinition of NEGATIVE_RESET on minsoc_bench_defines.v cannot affect other inclusions of ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=59 <div><strong>Rev 59 - rfajardo</strong> (2 file(s) modified)</div><div>undefinition of NEGATIVE_RESET on minsoc_bench_defines.v cannot affect other inclusions of ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br /> rfajardo Thu, 28 Apr 2011 21:59:30 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=59 Standard definitions depended on implementation order. Now, this should be ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=58 <div><strong>Rev 58 - rfajardo</strong> (2 file(s) modified)</div><div>Standard definitions depended on implementation order. Now, this should be ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br /> rfajardo Thu, 28 Apr 2011 21:50:11 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=58 1) Period calculations through 1/freq on testbench use now a ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=28 <div><strong>Rev 28 - rfajardo</strong> (4 file(s) modified)</div><div>1) Period calculations through 1/freq on testbench use now a ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/doc/howto.pdf<br />~ /minsoc/trunk/doc/src/howto.odt<br /> rfajardo Wed, 05 May 2010 14:50:01 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=28 Simulation library fpga_memory_primitives.v had an issue with its lpm_ram_dq module, ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=27 <div><strong>Rev 27 - rfajardo</strong> (1 file(s) modified)</div><div>Simulation library fpga_memory_primitives.v had an issue with its lpm_ram_dq module, ...</div>~ /minsoc/trunk/bench/verilog/sim_lib/fpga_memory_primitives.v<br /> rfajardo Tue, 20 Apr 2010 14:14:15 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=27 Ethernet testbench speed penalty solved. Now Ethernet of testbench and ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=17 <div><strong>Rev 17 - rfajardo</strong> (16 file(s) modified)</div><div>Ethernet testbench speed penalty solved. Now Ethernet of testbench and ...</div>- /minsoc/trunk/bench/verilog/eth_phy.v<br />- /minsoc/trunk/bench/verilog/eth_phy_defines.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/bench/verilog/sim_lib/fpga_memory_primitives.v<br />- /minsoc/trunk/bench/verilog/tb_eth_defines.v<br />~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />+ /minsoc/trunk/sim/bin/minsoc_memory.txt<br />- /minsoc/trunk/sim/bin/minsoc_memory_complete.txt<br />- /minsoc/trunk/sim/bin/minsoc_memory_fast.txt<br />+ /minsoc/trunk/sim/bin/minsoc_model.txt<br />- /minsoc/trunk/sim/bin/minsoc_model_complete.txt<br />- /minsoc/trunk/sim/bin/minsoc_model_fast.txt<br />~ /minsoc/trunk/sim/run/generate_bench<br /> rfajardo Tue, 17 Nov 2009 14:38:49 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=17 External interrupt processing was being run multiple times because: ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=11 <div><strong>Rev 11 - rfajardo</strong> (2 file(s) modified)</div><div>External interrupt processing was being run multiple times because:<br /> ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/sw/support/int.c<br /> rfajardo Fri, 23 Oct 2009 14:49:17 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=11 Added a file containing models for each FPGA memory instances ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=10 <div><strong>Rev 10 - rfajardo</strong> (7 file(s) modified)</div><div>Added a file containing models for each FPGA memory instances ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />+ /minsoc/trunk/bench/verilog/sim_lib<br />+ /minsoc/trunk/bench/verilog/sim_lib/fpga_memory_primitives.v<br />~ /minsoc/trunk/sim/bin/minsoc_memory_complete.txt<br />~ /minsoc/trunk/sim/bin/minsoc_memory_fast.txt<br />~ /minsoc/trunk/sim/bin/minsoc_model_complete.txt<br />~ /minsoc/trunk/sim/bin/minsoc_model_fast.txt<br /> rfajardo Fri, 09 Oct 2009 15:20:03 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=10 Tiny change to testbench gain: -uart_srx is ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=9 <div><strong>Rev 9 - rfajardo</strong> (1 file(s) modified)</div><div>Tiny change to testbench gain:<br /> -uart_srx is ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br /> rfajardo Wed, 07 Oct 2009 16:32:49 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=9 Cosmetic changes to minsoc_bench.v: -reset and clock ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=8 <div><strong>Rev 8 - rfajardo</strong> (1 file(s) modified)</div><div>Cosmetic changes to minsoc_bench.v:<br /> -reset and clock ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br /> rfajardo Wed, 07 Oct 2009 16:27:57 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=8 Some changes: -wb_cabs removed from minsoc_top.v and ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=7 <div><strong>Rev 7 - rfajardo</strong> (6 file(s) modified)</div><div>Some changes:<br /> -wb_cabs removed from minsoc_top.v and ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_onchip_ram.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_onchip_ram_top.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_tc_top.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br /> rfajardo Fri, 02 Oct 2009 15:56:44 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=7 minsoc_bench.v had a big memory declaration to load the firmware, ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=4 <div><strong>Rev 4 - rfajardo</strong> (4 file(s) modified)</div><div>minsoc_bench.v had a big memory declaration to load the firmware, ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />- /minsoc/trunk/bench/verilog/vpi/jp-io-vpi.vpi<br />~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br /> rfajardo Tue, 22 Sep 2009 10:23:31 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=4 First commit of project. Beta status: -testbench: ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=2 <div><strong>Rev 2 - rfajardo</strong> (92 file(s) modified)</div><div>First commit of project. Beta status:<br /> -testbench: ...</div>+ /minsoc/trunk/backend<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit.ucf<br />+ /minsoc/trunk/backend/spartan3e_starter_kit.ucf<br />+ /minsoc/trunk/bench<br />+ /minsoc/trunk/bench/verilog<br />+ /minsoc/trunk/bench/verilog/eth_phy.v<br />+ /minsoc/trunk/bench/verilog/eth_phy_defines.v<br />+ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />+ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />+ /minsoc/trunk/bench/verilog/minsoc_memory_model.v<br />+ /minsoc/trunk/bench/verilog/tb_eth_defines.v<br />+ /minsoc/trunk/bench/verilog/vpi<br />+ /minsoc/trunk/bench/verilog/vpi/dbg_comm_vpi.v<br />+ /minsoc/trunk/bench/verilog/vpi/jp-io-vpi.vpi<br />+ /minsoc/trunk/doc<br />+ /minsoc/trunk/doc/lgpl-3.0.txt<br />+ /minsoc/trunk/doc/minsoc.odt<br />+ /minsoc/trunk/doc/minsoc.pdf<br />+ /minsoc/trunk/rtl<br />+ /minsoc/trunk/rtl/verilog<br />+ /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_onchip_ram.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_onchip_ram_top.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/OR1K_startup_generic.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_clgen.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_defines.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_shift.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_top.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_tc_top.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_xilinx_internal_jtag.v<br />+ /minsoc/trunk/sim<br />+ /minsoc/trunk/sim/bin<br />+ /minsoc/trunk/sim/bin/minsoc_memory_complete.txt<br />+ /minsoc/trunk/sim/bin/minsoc_memory_fast.txt<br />+ /minsoc/trunk/sim/bin/minsoc_model_complete.txt<br />+ /minsoc/trunk/sim/bin/minsoc_model_fast.txt<br />+ /minsoc/trunk/sim/results<br />+ /minsoc/trunk/sim/results/wave.do.sav<br />+ /minsoc/trunk/sim/run<br />+ /minsoc/trunk/sim/run/generate_bench<br />+ /minsoc/trunk/sim/run/run_bench<br />+ /minsoc/trunk/sim/run/start_server<br />+ /minsoc/trunk/sw<br />+ /minsoc/trunk/sw/eth<br />+ /minsoc/trunk/sw/eth/eth.c<br />+ /minsoc/trunk/sw/eth/eth.h<br />+ /minsoc/trunk/sw/eth/Makefile<br />+ /minsoc/trunk/sw/support<br />+ /minsoc/trunk/sw/support/board.h<br />+ /minsoc/trunk/sw/support/except.S<br />+ /minsoc/trunk/sw/support/int.c<br />+ /minsoc/trunk/sw/support/int.h<br />+ /minsoc/trunk/sw/support/Makefile<br />+ /minsoc/trunk/sw/support/Makefile.inc<br />+ /minsoc/trunk/sw/support/mc.h<br />+ /minsoc/trunk/sw/support/orp.cfg<br />+ /minsoc/trunk/sw/support/orp.ld<br />+ /minsoc/trunk/sw/support/reset.S<br />+ /minsoc/trunk/sw/support/spr_defs.h<br />+ /minsoc/trunk/sw/support/support.c<br />+ /minsoc/trunk/sw/support/support.h<br />+ /minsoc/trunk/sw/support/uart.c<br />+ /minsoc/trunk/sw/support/uart.h<br />+ /minsoc/trunk/sw/support/vfnprintf.c<br />+ /minsoc/trunk/sw/support/vfnprintf.h<br />+ /minsoc/trunk/sw/uart<br />+ /minsoc/trunk/sw/uart/Makefile<br />+ /minsoc/trunk/sw/uart/uart.c<br />+ /minsoc/trunk/sw/uart/uart.h<br />+ /minsoc/trunk/sw/utils<br />+ /minsoc/trunk/sw/utils/bin2c.c<br />+ /minsoc/trunk/sw/utils/bin2flimg.c<br />+ /minsoc/trunk/sw/utils/bin2hex.c<br />+ /minsoc/trunk/sw/utils/bin2srec.c<br />+ /minsoc/trunk/sw/utils/bin2vmem.c<br />+ /minsoc/trunk/sw/utils/loader.c<br />+ /minsoc/trunk/sw/utils/Makefile<br />+ /minsoc/trunk/sw/utils/marksec<br />+ /minsoc/trunk/sw/utils/merge2srec<br />+ /minsoc/trunk/sw/utils/or32-idecode<br />+ /minsoc/trunk/sw/utils/or32-idecode/ansidecl.h<br />+ /minsoc/trunk/sw/utils/or32-idecode/bfd.h<br />+ /minsoc/trunk/sw/utils/or32-idecode/dis-asm.h<br />+ /minsoc/trunk/sw/utils/or32-idecode/example_input<br />+ /minsoc/trunk/sw/utils/or32-idecode/Makefile<br />+ /minsoc/trunk/sw/utils/or32-idecode/or32-dis.c<br />+ /minsoc/trunk/sw/utils/or32-idecode/or32-opc.c<br />+ /minsoc/trunk/sw/utils/or32-idecode/or32.h<br />+ /minsoc/trunk/sw/utils/or32-idecode/symcat.h<br /> rfajardo Fri, 18 Sep 2009 11:46:11 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2F&rev=2
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