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minsoc WebSVN RSS feed - minsoc https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2Fverilog%2Fminsoc_bench.v& Fri, 28 Jan 2022 02:56:26 +0100 FeedCreator 1.7.2 Tasks don't have parenthesis. This is only used for ports ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2Fverilog%2F&rev=162 <div><strong>Rev 162 - rfajardo</strong> (1 file(s) modified)</div><div>Tasks don't have parenthesis. This is only used for ports ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br /> rfajardo Fri, 20 Jan 2012 15:23:36 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2Fverilog%2F&rev=162 Merging differences of release candidate 1.0 revision 140:148 with trunk. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2Fverilog%2F&rev=149 <div><strong>Rev 149 - rfajardo</strong> (19 file(s) modified)</div><div>Merging differences of release candidate 1.0 revision 140:148 with trunk.</div>~ /minsoc/trunk<br />~ /minsoc/trunk/backend/altera_3c25_board/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/std/minsoc_bench_defines.v<br />+ /minsoc/trunk/backend/ug257<br />/minsoc/trunk/backend/ug257/board.h<br />/minsoc/trunk/backend/ug257/configure<br />/minsoc/trunk/backend/ug257/gcc-opt.mk<br />/minsoc/trunk/backend/ug257/minsoc_bench_defines.v<br />/minsoc/trunk/backend/ug257/minsoc_defines.v<br />/minsoc/trunk/backend/ug257/orp.ld<br />/minsoc/trunk/backend/ug257/ug257.ucf<br />~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/sim/run/run_bench<br />~ /minsoc/trunk/sw/drivers/uart.c<br />~ /minsoc/trunk/sw/eth/eth.c<br />~ /minsoc/trunk/sw/uart/uart.c<br />~ /minsoc/trunk/utils/setup/minsoc-install.sh<br /> rfajardo Mon, 28 Nov 2011 10:02:52 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2Fverilog%2F&rev=149 Merging with rc-1.0 revision 140. I doubt rc-1.0 will still ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2Fverilog%2F&rev=141 <div><strong>Rev 141 - rfajardo</strong> (32 file(s) modified)</div><div>Merging with rc-1.0 revision 140. I doubt rc-1.0 will still ...</div>~ /minsoc/trunk<br />~ /minsoc/trunk/backend/altera_3c25_board/configure<br />~ /minsoc/trunk/backend/altera_3c25_board/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/std/configure<br />~ /minsoc/trunk/backend/std/minsoc_bench_defines.v<br />/minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/prj/Makefile<br />- /minsoc/trunk/prj/scripts/altprj.sh<br />+ /minsoc/trunk/prj/scripts/altvhdprj.sh<br />+ /minsoc/trunk/prj/scripts/altvprj.sh<br />~ /minsoc/trunk/prj/scripts/simverilog.sh<br />~ /minsoc/trunk/prj/scripts/simvhdl.sh<br />~ /minsoc/trunk/prj/scripts/xilinxprj.sh<br />~ /minsoc/trunk/prj/src/ethmac.prj<br />~ /minsoc/trunk/sim/modelsim/compile_design.bat<br />~ /minsoc/trunk/sim/modelsim/prepare_modelsim.bat<br />~ /minsoc/trunk/sim/modelsim/run_sim.bat<br />~ /minsoc/trunk/sim/modelsim/run_sim.sh<br />~ /minsoc/trunk/sim/run/run_bench<br />~ /minsoc/trunk/sw/utils/bin2hex.c<br />~ /minsoc/trunk/syn/xilinx/setup.bat<br />~ /minsoc/trunk/utils/setup/beautify.sh<br />+ /minsoc/trunk/utils/setup/configure.sh<br />~ /minsoc/trunk/utils/setup/minsoc-install.sh<br />+ /minsoc/trunk/utils/setup/minsoc-setup.sh<br />~ /minsoc/trunk/utils/setup/required-cygwin-tools.txt<br /> rfajardo Tue, 22 Nov 2011 10:46:40 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2Fverilog%2F&rev=141 Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2Fverilog%2F&rev=133 <div><strong>Rev 133 - rfajardo</strong> (7 file(s) modified)</div><div>Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock ...</div>+ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_core.v<br />~ /minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj<br />~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.bat<br />~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.sh<br />~ /minsoc/branches/rc-1.0/sim/run/run_bench<br />~ /minsoc/branches/rc-1.0/sw/utils/bin2hex.c<br /> rfajardo Mon, 07 Nov 2011 09:48:11 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fbench%2Fverilog%2F&rev=133
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