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minsoc WebSVN RSS feed - minsoc https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2Fscripts%2Fsimvhdl.sh& Thu, 28 Mar 2024 20:50:23 +0100 FeedCreator 1.7.2 Enabling modelsim simulation for current project definition. vhdl and verilog projects ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2Fscripts%2F&rev=104 <div><strong>Rev 104 - rfajardo</strong> (7 file(s) modified)</div><div>Enabling modelsim simulation for current project definition.<br /> vhdl and verilog projects ...</div>~ /minsoc/trunk/prj/Makefile<br />- /minsoc/trunk/prj/scripts/simprj.sh<br />+ /minsoc/trunk/prj/scripts/simverilog.sh<br />+ /minsoc/trunk/prj/scripts/simvhdl.sh<br />~ /minsoc/trunk/sim/modelsim/compile_design.bat<br />~ /minsoc/trunk/sim/modelsim/compile_design.sh<br />~ /minsoc/trunk/sim/run/generate_bench<br /> rfajardo Wed, 19 Oct 2011 10:31:39 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2Fscripts%2F&rev=104
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