URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
Error creating feed file, please check write permissions.
minsoc
WebSVN RSS feed - minsoc
https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2Fxilinx%2F&
Thu, 28 Mar 2024 23:49:13 +0100
FeedCreator 1.7.2
-
As proposed by Javier Almansa automatically generated project files for ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2Fxilinx%2F&rev=97
<div><strong>Rev 97 - rfajardo</strong> (32 file(s) modified)</div><div>As proposed by Javier Almansa automatically generated project files for ...</div>~ /minsoc/trunk/backend/altera_3c25_board/configure<br />~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/trunk/backend/std/configure<br />- /minsoc/trunk/prj/altera/adbg_top.prj<br />- /minsoc/trunk/prj/altera/altera_virtual_jtag.prj<br />- /minsoc/trunk/prj/altera/ethmac.prj<br />- /minsoc/trunk/prj/altera/jtag_top.prj<br />- /minsoc/trunk/prj/altera/minsoc_bench.prj<br />- /minsoc/trunk/prj/altera/minsoc_top.prj<br />- /minsoc/trunk/prj/altera/or1200_top.prj<br />- /minsoc/trunk/prj/altera/uart_top.prj<br />- /minsoc/trunk/prj/sim/adbg_top.src<br />- /minsoc/trunk/prj/sim/ethmac.src<br />- /minsoc/trunk/prj/sim/jtag_top.src<br />- /minsoc/trunk/prj/sim/minsoc.src<br />- /minsoc/trunk/prj/sim/minsoc_top.src<br />- /minsoc/trunk/prj/sim/or1200_top.src<br />- /minsoc/trunk/prj/sim/uart_top.src<br />- /minsoc/trunk/prj/xilinx/adbg_top.prj<br />- /minsoc/trunk/prj/xilinx/adbg_top.xst<br />- /minsoc/trunk/prj/xilinx/ethmac.prj<br />- /minsoc/trunk/prj/xilinx/ethmac.xst<br />- /minsoc/trunk/prj/xilinx/jtag_top.prj<br />- /minsoc/trunk/prj/xilinx/jtag_top.xst<br />- /minsoc/trunk/prj/xilinx/minsoc_top.prj<br />- /minsoc/trunk/prj/xilinx/minsoc_top.xst<br />- /minsoc/trunk/prj/xilinx/or1200_top.prj<br />- /minsoc/trunk/prj/xilinx/or1200_top.xst<br />- /minsoc/trunk/prj/xilinx/uart_top.prj<br />- /minsoc/trunk/prj/xilinx/uart_top.xst<br />
rfajardo
Mon, 12 Sep 2011 08:54:47 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2Fxilinx%2F&rev=97
-
prj/scripts/: Changing scripts not to include multiple timescale.v files from ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2Fxilinx%2F&rev=91
<div><strong>Rev 91 - rfajardo</strong> (5 file(s) modified)</div><div>prj/scripts/: Changing scripts not to include multiple timescale.v files from ...</div>~ /minsoc/trunk/prj/scripts/simprj.sh<br />~ /minsoc/trunk/prj/scripts/xilinxprj.sh<br />~ /minsoc/trunk/prj/sim/minsoc.src<br />~ /minsoc/trunk/prj/sim/minsoc_top.src<br />~ /minsoc/trunk/prj/xilinx/minsoc_top.prj<br />
rfajardo
Wed, 07 Sep 2011 08:47:21 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2Fxilinx%2F&rev=91
-
After minsoc_top.prj update, make regenerated src and xst files.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2Fxilinx%2F&rev=90
<div><strong>Rev 90 - rfajardo</strong> (3 file(s) modified)</div><div>After minsoc_top.prj update, make regenerated src and xst files.</div>~ /minsoc/trunk/prj/sim/minsoc.src<br />~ /minsoc/trunk/prj/sim/minsoc_top.src<br />~ /minsoc/trunk/prj/xilinx/minsoc_top.xst<br />
rfajardo
Tue, 06 Sep 2011 17:17:27 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2Fxilinx%2F&rev=90
-
Project structure, Xilinx Makefiles and simulation working.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2Fxilinx%2F&rev=88
<div><strong>Rev 88 - rfajardo</strong> (20 file(s) modified)</div><div>Project structure, Xilinx Makefiles and simulation working.</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_defines.v<br />~ /minsoc/trunk/prj/Makefile<br />~ /minsoc/trunk/prj/scripts/simprj.sh<br />~ /minsoc/trunk/prj/scripts/xilinxprj.sh<br />~ /minsoc/trunk/prj/scripts/xilinxxst.sh<br />~ /minsoc/trunk/prj/sim/minsoc.src<br />~ /minsoc/trunk/prj/sim/minsoc_top.src<br />+ /minsoc/trunk/prj/src/minsoc_bench.prj<br />~ /minsoc/trunk/prj/src/minsoc_top.prj<br />~ /minsoc/trunk/prj/xilinx/adbg_top.xst<br />~ /minsoc/trunk/prj/xilinx/ethmac.xst<br />~ /minsoc/trunk/prj/xilinx/jtag_top.xst<br />~ /minsoc/trunk/prj/xilinx/minsoc_top.prj<br />~ /minsoc/trunk/prj/xilinx/minsoc_top.xst<br />~ /minsoc/trunk/prj/xilinx/or1200_top.xst<br />~ /minsoc/trunk/prj/xilinx/uart_top.xst<br />~ /minsoc/trunk/rtl/verilog/xilinx_dcm.v<br />~ /minsoc/trunk/syn/xilinx/Makefile<br />
rfajardo
Tue, 06 Sep 2011 16:54:44 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2Fxilinx%2F&rev=88
-
Central project definition under prj. Synthesis and simulation take their ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2Fxilinx%2F&rev=85
<div><strong>Rev 85 - rfajardo</strong> (55 file(s) modified)</div><div>Central project definition under prj. Synthesis and simulation take their ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/trunk/backend/std/configure<br />+ /minsoc/trunk/prj<br />+ /minsoc/trunk/prj/altera<br />+ /minsoc/trunk/prj/Makefile<br />+ /minsoc/trunk/prj/scripts<br />+ /minsoc/trunk/prj/scripts/simprj.sh<br />+ /minsoc/trunk/prj/scripts/xilinxprj.sh<br />+ /minsoc/trunk/prj/scripts/xilinxxst.sh<br />+ /minsoc/trunk/prj/sim<br />+ /minsoc/trunk/prj/sim/adbg_top.src<br />+ /minsoc/trunk/prj/sim/ethmac.src<br />+ /minsoc/trunk/prj/sim/jtag_top.src<br />+ /minsoc/trunk/prj/sim/minsoc.src<br />+ /minsoc/trunk/prj/sim/minsoc_top.src<br />+ /minsoc/trunk/prj/sim/or1200_top.src<br />+ /minsoc/trunk/prj/sim/uart_top.src<br />+ /minsoc/trunk/prj/src<br />+ /minsoc/trunk/prj/src/adbg_top.prj<br />+ /minsoc/trunk/prj/src/blackboxes<br />+ /minsoc/trunk/prj/src/blackboxes/ethmac.v<br />- /minsoc/trunk/prj/src/blackboxes/eth_top.v<br />+ /minsoc/trunk/prj/src/ethmac.prj<br />+ /minsoc/trunk/prj/src/jtag_top.prj<br />+ /minsoc/trunk/prj/src/minsoc_top.prj<br />+ /minsoc/trunk/prj/src/or1200_top.prj<br />+ /minsoc/trunk/prj/src/uart_top.prj<br />+ /minsoc/trunk/prj/xilinx<br />+ /minsoc/trunk/prj/xilinx/adbg_top.prj<br />+ /minsoc/trunk/prj/xilinx/adbg_top.xst<br />+ /minsoc/trunk/prj/xilinx/ethmac.prj<br />+ /minsoc/trunk/prj/xilinx/ethmac.xst<br />+ /minsoc/trunk/prj/xilinx/jtag_top.prj<br />+ /minsoc/trunk/prj/xilinx/jtag_top.xst<br />+ /minsoc/trunk/prj/xilinx/minsoc_top.prj<br />+ /minsoc/trunk/prj/xilinx/minsoc_top.xst<br />+ /minsoc/trunk/prj/xilinx/or1200_top.prj<br />+ /minsoc/trunk/prj/xilinx/or1200_top.xst<br />+ /minsoc/trunk/prj/xilinx/uart_top.prj<br />+ /minsoc/trunk/prj/xilinx/uart_top.xst<br />- /minsoc/trunk/sim/bin<br />~ /minsoc/trunk/sim/modelsim/compile_design.bat<br />~ /minsoc/trunk/sim/modelsim/compile_design.sh<br />~ /minsoc/trunk/sim/run/generate_bench<br />- /minsoc/trunk/syn/blackboxes<br />- /minsoc/trunk/syn/buildSupport/adbg_top.prj<br />- /minsoc/trunk/syn/buildSupport/eth_top.prj<br />- /minsoc/trunk/syn/buildSupport/minsoc_top.prj<br />- /minsoc/trunk/syn/buildSupport/or1200_top.prj<br />- /minsoc/trunk/syn/buildSupport/uart_top.prj<br />- /minsoc/trunk/syn/src<br />+ /minsoc/trunk/syn/xilinx<br />+ /minsoc/trunk/syn/xilinx/Makefile<br />
rfajardo
Tue, 06 Sep 2011 15:34:18 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fprj%2Fxilinx%2F&rev=85
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.