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https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Fmodelsim%2F&
Thu, 28 Mar 2024 13:44:39 +0100FeedCreator 1.7.2Makefile does not automatic clean anymore. In Windows rm -f ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Fmodelsim%2F&rev=73
<div><strong>Rev 73 - rfajardo</strong> (5 file(s) modified)</div><div>Makefile does not automatic clean anymore. In Windows rm -f ...</div>~ /minsoc/trunk/sim/modelsim/compile_design.bat<br />~ /minsoc/trunk/sim/modelsim/prepare_modelsim.bat<br />~ /minsoc/trunk/sim/modelsim/run_sim.bat<br />+ /minsoc/trunk/syn/setup.bat<br />~ /minsoc/trunk/syn/src/Makefile<br />rfajardoTue, 10 May 2011 13:52:00 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Fmodelsim%2F&rev=73Adding Windows batch files to run a Modelsim simulation.
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https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Fmodelsim%2F&rev=72
<div><strong>Rev 72 - rfajardo</strong> (3 file(s) modified)</div><div>Adding Windows batch files to run a Modelsim simulation. <br />
...</div>+ /minsoc/trunk/sim/modelsim/compile_design.bat<br />+ /minsoc/trunk/sim/modelsim/prepare_modelsim.bat<br />+ /minsoc/trunk/sim/modelsim/run_sim.bat<br />rfajardoTue, 10 May 2011 12:50:07 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Fmodelsim%2F&rev=72Including a global timescale under minsoc/rtl/verilog to control simulation. It ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Fmodelsim%2F&rev=70
<div><strong>Rev 70 - rfajardo</strong> (10 file(s) modified)</div><div>Including a global timescale under minsoc/rtl/verilog to control simulation. It ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/std/minsoc_bench_defines.v<br />+ /minsoc/trunk/rtl/verilog/timescale.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />+ /minsoc/trunk/sim/modelsim<br />+ /minsoc/trunk/sim/modelsim/compile_design.sh<br />+ /minsoc/trunk/sim/modelsim/prepare_modelsim.sh<br />+ /minsoc/trunk/sim/modelsim/run_sim.sh<br />rfajardoTue, 10 May 2011 10:06:07 +0100https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Fmodelsim%2F&rev=70