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minsoc WebSVN RSS feed - minsoc https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Fmodelsim%2Fcompile_design.sh& Tue, 19 Mar 2024 09:28:55 +0100 FeedCreator 1.7.2 Enabling modelsim simulation for current project definition. vhdl and verilog projects ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Fmodelsim%2F&rev=104 <div><strong>Rev 104 - rfajardo</strong> (7 file(s) modified)</div><div>Enabling modelsim simulation for current project definition.<br /> vhdl and verilog projects ...</div>~ /minsoc/trunk/prj/Makefile<br />- /minsoc/trunk/prj/scripts/simprj.sh<br />+ /minsoc/trunk/prj/scripts/simverilog.sh<br />+ /minsoc/trunk/prj/scripts/simvhdl.sh<br />~ /minsoc/trunk/sim/modelsim/compile_design.bat<br />~ /minsoc/trunk/sim/modelsim/compile_design.sh<br />~ /minsoc/trunk/sim/run/generate_bench<br /> rfajardo Wed, 19 Oct 2011 10:31:39 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Fmodelsim%2F&rev=104 Central project definition under prj. Synthesis and simulation take their ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Fmodelsim%2F&rev=85 <div><strong>Rev 85 - rfajardo</strong> (55 file(s) modified)</div><div>Central project definition under prj. Synthesis and simulation take their ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/trunk/backend/std/configure<br />+ /minsoc/trunk/prj<br />+ /minsoc/trunk/prj/altera<br />+ /minsoc/trunk/prj/Makefile<br />+ /minsoc/trunk/prj/scripts<br />+ /minsoc/trunk/prj/scripts/simprj.sh<br />+ /minsoc/trunk/prj/scripts/xilinxprj.sh<br />+ /minsoc/trunk/prj/scripts/xilinxxst.sh<br />+ /minsoc/trunk/prj/sim<br />+ /minsoc/trunk/prj/sim/adbg_top.src<br />+ /minsoc/trunk/prj/sim/ethmac.src<br />+ /minsoc/trunk/prj/sim/jtag_top.src<br />+ /minsoc/trunk/prj/sim/minsoc.src<br />+ /minsoc/trunk/prj/sim/minsoc_top.src<br />+ /minsoc/trunk/prj/sim/or1200_top.src<br />+ /minsoc/trunk/prj/sim/uart_top.src<br />+ /minsoc/trunk/prj/src<br />+ /minsoc/trunk/prj/src/adbg_top.prj<br />+ /minsoc/trunk/prj/src/blackboxes<br />+ /minsoc/trunk/prj/src/blackboxes/ethmac.v<br />- /minsoc/trunk/prj/src/blackboxes/eth_top.v<br />+ /minsoc/trunk/prj/src/ethmac.prj<br />+ /minsoc/trunk/prj/src/jtag_top.prj<br />+ /minsoc/trunk/prj/src/minsoc_top.prj<br />+ /minsoc/trunk/prj/src/or1200_top.prj<br />+ /minsoc/trunk/prj/src/uart_top.prj<br />+ /minsoc/trunk/prj/xilinx<br />+ /minsoc/trunk/prj/xilinx/adbg_top.prj<br />+ /minsoc/trunk/prj/xilinx/adbg_top.xst<br />+ /minsoc/trunk/prj/xilinx/ethmac.prj<br />+ /minsoc/trunk/prj/xilinx/ethmac.xst<br />+ /minsoc/trunk/prj/xilinx/jtag_top.prj<br />+ /minsoc/trunk/prj/xilinx/jtag_top.xst<br />+ /minsoc/trunk/prj/xilinx/minsoc_top.prj<br />+ /minsoc/trunk/prj/xilinx/minsoc_top.xst<br />+ /minsoc/trunk/prj/xilinx/or1200_top.prj<br />+ /minsoc/trunk/prj/xilinx/or1200_top.xst<br />+ /minsoc/trunk/prj/xilinx/uart_top.prj<br />+ /minsoc/trunk/prj/xilinx/uart_top.xst<br />- /minsoc/trunk/sim/bin<br />~ /minsoc/trunk/sim/modelsim/compile_design.bat<br />~ /minsoc/trunk/sim/modelsim/compile_design.sh<br />~ /minsoc/trunk/sim/run/generate_bench<br />- /minsoc/trunk/syn/blackboxes<br />- /minsoc/trunk/syn/buildSupport/adbg_top.prj<br />- /minsoc/trunk/syn/buildSupport/eth_top.prj<br />- /minsoc/trunk/syn/buildSupport/minsoc_top.prj<br />- /minsoc/trunk/syn/buildSupport/or1200_top.prj<br />- /minsoc/trunk/syn/buildSupport/uart_top.prj<br />- /minsoc/trunk/syn/src<br />+ /minsoc/trunk/syn/xilinx<br />+ /minsoc/trunk/syn/xilinx/Makefile<br /> rfajardo Tue, 06 Sep 2011 15:34:18 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Fmodelsim%2F&rev=85 Including a global timescale under minsoc/rtl/verilog to control simulation. It ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Fmodelsim%2F&rev=70 <div><strong>Rev 70 - rfajardo</strong> (10 file(s) modified)</div><div>Including a global timescale under minsoc/rtl/verilog to control simulation. It ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/std/minsoc_bench_defines.v<br />+ /minsoc/trunk/rtl/verilog/timescale.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />+ /minsoc/trunk/sim/modelsim<br />+ /minsoc/trunk/sim/modelsim/compile_design.sh<br />+ /minsoc/trunk/sim/modelsim/prepare_modelsim.sh<br />+ /minsoc/trunk/sim/modelsim/run_sim.sh<br /> rfajardo Tue, 10 May 2011 10:06:07 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Fmodelsim%2F&rev=70
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