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minsoc WebSVN RSS feed - minsoc https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Frun%2F& Thu, 06 Aug 2020 16:59:09 +0100 FeedCreator 1.7.2 Merging with rc-1.0 revision 140. I doubt rc-1.0 will still ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Frun%2F&rev=141 <div><strong>Rev 141 - rfajardo</strong> (32 file(s) modified)</div><div>Merging with rc-1.0 revision 140. I doubt rc-1.0 will still ...</div>~ /minsoc/trunk<br />~ /minsoc/trunk/backend/altera_3c25_board/configure<br />~ /minsoc/trunk/backend/altera_3c25_board/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/std/configure<br />~ /minsoc/trunk/backend/std/minsoc_bench_defines.v<br />/minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/prj/Makefile<br />- /minsoc/trunk/prj/scripts/altprj.sh<br />+ /minsoc/trunk/prj/scripts/altvhdprj.sh<br />+ /minsoc/trunk/prj/scripts/altvprj.sh<br />~ /minsoc/trunk/prj/scripts/simverilog.sh<br />~ /minsoc/trunk/prj/scripts/simvhdl.sh<br />~ /minsoc/trunk/prj/scripts/xilinxprj.sh<br />~ /minsoc/trunk/prj/src/ethmac.prj<br />~ /minsoc/trunk/sim/modelsim/compile_design.bat<br />~ /minsoc/trunk/sim/modelsim/prepare_modelsim.bat<br />~ /minsoc/trunk/sim/modelsim/run_sim.bat<br />~ /minsoc/trunk/sim/modelsim/run_sim.sh<br />~ /minsoc/trunk/sim/run/run_bench<br />~ /minsoc/trunk/sw/utils/bin2hex.c<br />~ /minsoc/trunk/syn/xilinx/setup.bat<br />~ /minsoc/trunk/utils/setup/beautify.sh<br />+ /minsoc/trunk/utils/setup/configure.sh<br />~ /minsoc/trunk/utils/setup/minsoc-install.sh<br />+ /minsoc/trunk/utils/setup/minsoc-setup.sh<br />~ /minsoc/trunk/utils/setup/required-cygwin-tools.txt<br /> rfajardo Tue, 22 Nov 2011 10:46:40 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Frun%2F&rev=141 Enabling modelsim simulation for current project definition. vhdl and verilog projects ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Frun%2F&rev=104 <div><strong>Rev 104 - rfajardo</strong> (7 file(s) modified)</div><div>Enabling modelsim simulation for current project definition.<br /> vhdl and verilog projects ...</div>~ /minsoc/trunk/prj/Makefile<br />- /minsoc/trunk/prj/scripts/simprj.sh<br />+ /minsoc/trunk/prj/scripts/simverilog.sh<br />+ /minsoc/trunk/prj/scripts/simvhdl.sh<br />~ /minsoc/trunk/sim/modelsim/compile_design.bat<br />~ /minsoc/trunk/sim/modelsim/compile_design.sh<br />~ /minsoc/trunk/sim/run/generate_bench<br /> rfajardo Wed, 19 Oct 2011 10:31:39 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Frun%2F&rev=104 Central project definition under prj. Synthesis and simulation take their ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Frun%2F&rev=85 <div><strong>Rev 85 - rfajardo</strong> (55 file(s) modified)</div><div>Central project definition under prj. Synthesis and simulation take their ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/trunk/backend/std/configure<br />+ /minsoc/trunk/prj<br />+ /minsoc/trunk/prj/altera<br />+ /minsoc/trunk/prj/Makefile<br />+ /minsoc/trunk/prj/scripts<br />+ /minsoc/trunk/prj/scripts/simprj.sh<br />+ /minsoc/trunk/prj/scripts/xilinxprj.sh<br />+ /minsoc/trunk/prj/scripts/xilinxxst.sh<br />+ /minsoc/trunk/prj/sim<br />+ /minsoc/trunk/prj/sim/adbg_top.src<br />+ /minsoc/trunk/prj/sim/ethmac.src<br />+ /minsoc/trunk/prj/sim/jtag_top.src<br />+ /minsoc/trunk/prj/sim/minsoc.src<br />+ /minsoc/trunk/prj/sim/minsoc_top.src<br />+ /minsoc/trunk/prj/sim/or1200_top.src<br />+ /minsoc/trunk/prj/sim/uart_top.src<br />+ /minsoc/trunk/prj/src<br />+ /minsoc/trunk/prj/src/adbg_top.prj<br />+ /minsoc/trunk/prj/src/blackboxes<br />+ /minsoc/trunk/prj/src/blackboxes/ethmac.v<br />- /minsoc/trunk/prj/src/blackboxes/eth_top.v<br />+ /minsoc/trunk/prj/src/ethmac.prj<br />+ /minsoc/trunk/prj/src/jtag_top.prj<br />+ /minsoc/trunk/prj/src/minsoc_top.prj<br />+ /minsoc/trunk/prj/src/or1200_top.prj<br />+ /minsoc/trunk/prj/src/uart_top.prj<br />+ /minsoc/trunk/prj/xilinx<br />+ /minsoc/trunk/prj/xilinx/adbg_top.prj<br />+ /minsoc/trunk/prj/xilinx/adbg_top.xst<br />+ /minsoc/trunk/prj/xilinx/ethmac.prj<br />+ /minsoc/trunk/prj/xilinx/ethmac.xst<br />+ /minsoc/trunk/prj/xilinx/jtag_top.prj<br />+ /minsoc/trunk/prj/xilinx/jtag_top.xst<br />+ /minsoc/trunk/prj/xilinx/minsoc_top.prj<br />+ /minsoc/trunk/prj/xilinx/minsoc_top.xst<br />+ /minsoc/trunk/prj/xilinx/or1200_top.prj<br />+ /minsoc/trunk/prj/xilinx/or1200_top.xst<br />+ /minsoc/trunk/prj/xilinx/uart_top.prj<br />+ /minsoc/trunk/prj/xilinx/uart_top.xst<br />- /minsoc/trunk/sim/bin<br />~ /minsoc/trunk/sim/modelsim/compile_design.bat<br />~ /minsoc/trunk/sim/modelsim/compile_design.sh<br />~ /minsoc/trunk/sim/run/generate_bench<br />- /minsoc/trunk/syn/blackboxes<br />- /minsoc/trunk/syn/buildSupport/adbg_top.prj<br />- /minsoc/trunk/syn/buildSupport/eth_top.prj<br />- /minsoc/trunk/syn/buildSupport/minsoc_top.prj<br />- /minsoc/trunk/syn/buildSupport/or1200_top.prj<br />- /minsoc/trunk/syn/buildSupport/uart_top.prj<br />- /minsoc/trunk/syn/src<br />+ /minsoc/trunk/syn/xilinx<br />+ /minsoc/trunk/syn/xilinx/Makefile<br /> rfajardo Tue, 06 Sep 2011 15:34:18 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Frun%2F&rev=85 Selection of memory model or implementation memory is now made ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Frun%2F&rev=60 <div><strong>Rev 60 - rfajardo</strong> (8 file(s) modified)</div><div>Selection of memory model or implementation memory is now made ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/bench/verilog/minsoc_memory_model.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />- /minsoc/trunk/sim/bin/minsoc_memory.txt<br />- /minsoc/trunk/sim/bin/minsoc_model.txt<br />+ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />~ /minsoc/trunk/sim/run/generate_bench<br /> rfajardo Thu, 28 Apr 2011 22:44:09 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Frun%2F&rev=60 start_server changed: '-t' option of adv_jtag_bridge for vpi connection on ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Frun%2F&rev=34 <div><strong>Rev 34 - rfajardo</strong> (7 file(s) modified)</div><div>start_server changed: '-t' option of adv_jtag_bridge for vpi connection on ...</div>~ /minsoc/trunk/doc/FAQ.pdf<br />~ /minsoc/trunk/doc/INSTALL.pdf<br />~ /minsoc/trunk/doc/src/FAQ.odt<br />~ /minsoc/trunk/doc/src/INSTALL.odt<br />~ /minsoc/trunk/doc/src/synthesis_examples.odt<br />~ /minsoc/trunk/doc/synthesis_examples.pdf<br />~ /minsoc/trunk/sim/run/start_server<br /> rfajardo Fri, 15 Oct 2010 14:35:25 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Frun%2F&rev=34 minsoc SoC documentation had 2 small typo corrections. Performance penalty ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Frun%2F&rev=30 <div><strong>Rev 30 - rfajardo</strong> (7 file(s) modified)</div><div>minsoc SoC documentation had 2 small typo corrections. Performance penalty ...</div>~ /minsoc/trunk/doc/howto.pdf<br />~ /minsoc/trunk/doc/minsoc.pdf<br />~ /minsoc/trunk/doc/src/howto.odt<br />~ /minsoc/trunk/doc/src/minsoc.odt<br />~ /minsoc/trunk/sim/run/generate_bench<br />~ /minsoc/trunk/sim/run/run_bench<br />~ /minsoc/trunk/sim/run/start_server<br /> rfajardo Thu, 17 Jun 2010 09:54:28 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Frun%2F&rev=30 Ethernet testbench speed penalty solved. Now Ethernet of testbench and ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Frun%2F&rev=17 <div><strong>Rev 17 - rfajardo</strong> (16 file(s) modified)</div><div>Ethernet testbench speed penalty solved. Now Ethernet of testbench and ...</div>- /minsoc/trunk/bench/verilog/eth_phy.v<br />- /minsoc/trunk/bench/verilog/eth_phy_defines.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/bench/verilog/sim_lib/fpga_memory_primitives.v<br />- /minsoc/trunk/bench/verilog/tb_eth_defines.v<br />~ /minsoc/trunk/doc/minsoc.odt<br />~ /minsoc/trunk/doc/minsoc.pdf<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />+ /minsoc/trunk/sim/bin/minsoc_memory.txt<br />- /minsoc/trunk/sim/bin/minsoc_memory_complete.txt<br />- /minsoc/trunk/sim/bin/minsoc_memory_fast.txt<br />+ /minsoc/trunk/sim/bin/minsoc_model.txt<br />- /minsoc/trunk/sim/bin/minsoc_model_complete.txt<br />- /minsoc/trunk/sim/bin/minsoc_model_fast.txt<br />~ /minsoc/trunk/sim/run/generate_bench<br /> rfajardo Tue, 17 Nov 2009 14:38:49 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Frun%2F&rev=17 First commit of project. Beta status: -testbench: ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Frun%2F&rev=2 <div><strong>Rev 2 - rfajardo</strong> (92 file(s) modified)</div><div>First commit of project. Beta status:<br /> -testbench: ...</div>+ /minsoc/trunk/backend<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit.ucf<br />+ /minsoc/trunk/backend/spartan3e_starter_kit.ucf<br />+ /minsoc/trunk/bench<br />+ /minsoc/trunk/bench/verilog<br />+ /minsoc/trunk/bench/verilog/eth_phy.v<br />+ /minsoc/trunk/bench/verilog/eth_phy_defines.v<br />+ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />+ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />+ /minsoc/trunk/bench/verilog/minsoc_memory_model.v<br />+ /minsoc/trunk/bench/verilog/tb_eth_defines.v<br />+ /minsoc/trunk/bench/verilog/vpi<br />+ /minsoc/trunk/bench/verilog/vpi/dbg_comm_vpi.v<br />+ /minsoc/trunk/bench/verilog/vpi/jp-io-vpi.vpi<br />+ /minsoc/trunk/doc<br />+ /minsoc/trunk/doc/lgpl-3.0.txt<br />+ /minsoc/trunk/doc/minsoc.odt<br />+ /minsoc/trunk/doc/minsoc.pdf<br />+ /minsoc/trunk/rtl<br />+ /minsoc/trunk/rtl/verilog<br />+ /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_onchip_ram.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_onchip_ram_top.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/OR1K_startup_generic.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_clgen.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_defines.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_shift.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_startup/spi_top.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_tc_top.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_xilinx_internal_jtag.v<br />+ /minsoc/trunk/sim<br />+ /minsoc/trunk/sim/bin<br />+ /minsoc/trunk/sim/bin/minsoc_memory_complete.txt<br />+ /minsoc/trunk/sim/bin/minsoc_memory_fast.txt<br />+ /minsoc/trunk/sim/bin/minsoc_model_complete.txt<br />+ /minsoc/trunk/sim/bin/minsoc_model_fast.txt<br />+ /minsoc/trunk/sim/results<br />+ /minsoc/trunk/sim/results/wave.do.sav<br />+ /minsoc/trunk/sim/run<br />+ /minsoc/trunk/sim/run/generate_bench<br />+ /minsoc/trunk/sim/run/run_bench<br />+ /minsoc/trunk/sim/run/start_server<br />+ /minsoc/trunk/sw<br />+ /minsoc/trunk/sw/eth<br />+ /minsoc/trunk/sw/eth/eth.c<br />+ /minsoc/trunk/sw/eth/eth.h<br />+ /minsoc/trunk/sw/eth/Makefile<br />+ /minsoc/trunk/sw/support<br />+ /minsoc/trunk/sw/support/board.h<br />+ /minsoc/trunk/sw/support/except.S<br />+ /minsoc/trunk/sw/support/int.c<br />+ /minsoc/trunk/sw/support/int.h<br />+ /minsoc/trunk/sw/support/Makefile<br />+ /minsoc/trunk/sw/support/Makefile.inc<br />+ /minsoc/trunk/sw/support/mc.h<br />+ /minsoc/trunk/sw/support/orp.cfg<br />+ /minsoc/trunk/sw/support/orp.ld<br />+ /minsoc/trunk/sw/support/reset.S<br />+ /minsoc/trunk/sw/support/spr_defs.h<br />+ /minsoc/trunk/sw/support/support.c<br />+ /minsoc/trunk/sw/support/support.h<br />+ /minsoc/trunk/sw/support/uart.c<br />+ /minsoc/trunk/sw/support/uart.h<br />+ /minsoc/trunk/sw/support/vfnprintf.c<br />+ /minsoc/trunk/sw/support/vfnprintf.h<br />+ /minsoc/trunk/sw/uart<br />+ /minsoc/trunk/sw/uart/Makefile<br />+ /minsoc/trunk/sw/uart/uart.c<br />+ /minsoc/trunk/sw/uart/uart.h<br />+ /minsoc/trunk/sw/utils<br />+ /minsoc/trunk/sw/utils/bin2c.c<br />+ /minsoc/trunk/sw/utils/bin2flimg.c<br />+ /minsoc/trunk/sw/utils/bin2hex.c<br />+ /minsoc/trunk/sw/utils/bin2srec.c<br />+ /minsoc/trunk/sw/utils/bin2vmem.c<br />+ /minsoc/trunk/sw/utils/loader.c<br />+ /minsoc/trunk/sw/utils/Makefile<br />+ /minsoc/trunk/sw/utils/marksec<br />+ /minsoc/trunk/sw/utils/merge2srec<br />+ /minsoc/trunk/sw/utils/or32-idecode<br />+ /minsoc/trunk/sw/utils/or32-idecode/ansidecl.h<br />+ /minsoc/trunk/sw/utils/or32-idecode/bfd.h<br />+ /minsoc/trunk/sw/utils/or32-idecode/dis-asm.h<br />+ /minsoc/trunk/sw/utils/or32-idecode/example_input<br />+ /minsoc/trunk/sw/utils/or32-idecode/Makefile<br />+ /minsoc/trunk/sw/utils/or32-idecode/or32-dis.c<br />+ /minsoc/trunk/sw/utils/or32-idecode/or32-opc.c<br />+ /minsoc/trunk/sw/utils/or32-idecode/or32.h<br />+ /minsoc/trunk/sw/utils/or32-idecode/symcat.h<br /> rfajardo Fri, 18 Sep 2009 11:46:11 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Fsim%2Frun%2F&rev=2
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