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https://opencores.org/websvn//websvn/listing?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&
Fri, 29 Mar 2024 09:02:47 +0100FeedCreator 1.7.2adjusted core instantiation to new core module name
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=40
<div><strong>Rev 40 - JonasDC</strong> (1 file(s) modified)</div><div>adjusted core instantiation to new core module name</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />JonasDCTue, 13 Nov 2012 08:31:43 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=40changed files to remove warnings from synthesis
last cell logic is ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=39
<div><strong>Rev 39 - JonasDC</strong> (8 file(s) modified)</div><div>changed files to remove warnings from synthesis<br />
last cell logic is ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/autorun_cntrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_last_cell_logic.vhd<br />JonasDCMon, 12 Nov 2012 21:18:13 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=39deprecated design files because of new pipeline structure, will be ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=38
<div><strong>Rev 38 - JonasDC</strong> (6 file(s) modified)</div><div>deprecated design files because of new pipeline structure, will be ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/systolic_pipeline.vhd<br />JonasDCMon, 12 Nov 2012 15:44:05 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=38changed names of some generics of the multiplier.
moved the parameters ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=37
<div><strong>Rev 37 - JonasDC</strong> (6 file(s) modified)</div><div>changed names of some generics of the multiplier.<br />
moved the parameters ...</div>~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_multiplier.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />JonasDCThu, 08 Nov 2012 18:46:15 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=37found bug in new pipeline structure, now working properly. (tested ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=36
<div><strong>Rev 36 - JonasDC</strong> (2 file(s) modified)</div><div>found bug in new pipeline structure, now working properly. (tested ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />JonasDCWed, 07 Nov 2012 22:36:19 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=36new test values, 1st exponentiation gives error on result with ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=35
<div><strong>Rev 35 - JonasDC</strong> (1 file(s) modified)</div><div>new test values, 1st exponentiation gives error on result with ...</div>~ /mod_sim_exp/trunk/sim/src/sim_input.txt<br />JonasDCWed, 07 Nov 2012 20:08:23 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=35operand memory now supports custom operand widths, the internal memory ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=34
<div><strong>Rev 34 - JonasDC</strong> (3 file(s) modified)</div><div>operand memory now supports custom operand widths, the internal memory ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />JonasDCWed, 07 Nov 2012 19:01:11 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=34default pipeline changed to old version, there seems to be ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=33
<div><strong>Rev 33 - JonasDC</strong> (1 file(s) modified)</div><div>default pipeline changed to old version, there seems to be ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />JonasDCWed, 07 Nov 2012 16:11:50 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=33new systolic pipeline structure now has split pipeline support, tested ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=32
<div><strong>Rev 32 - JonasDC</strong> (3 file(s) modified)</div><div>new systolic pipeline structure now has split pipeline support, tested ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_multiplier.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />JonasDCWed, 07 Nov 2012 15:12:34 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=32put first cell logic of the pipeline in a separate ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=31
<div><strong>Rev 31 - JonasDC</strong> (4 file(s) modified)</div><div>put first cell logic of the pipeline in a separate ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_first_cell_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />JonasDCWed, 07 Nov 2012 10:01:55 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=31put last cell logic of the pipeline in a separate ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=30
<div><strong>Rev 30 - JonasDC</strong> (4 file(s) modified)</div><div>put last cell logic of the pipeline in a separate ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_last_cell_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />JonasDCWed, 07 Nov 2012 09:37:37 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=30added software for generation of test input for the tesbenches
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=29
<div><strong>Rev 29 - JonasDC</strong> (21 file(s) modified)</div><div>added software for generation of test input for the tesbenches</div>+ /mod_sim_exp/trunk/sw<br />+ /mod_sim_exp/trunk/sw/ModExp<br />+ /mod_sim_exp/trunk/sw/ModExp/.cproject<br />+ /mod_sim_exp/trunk/sw/ModExp/.project<br />+ /mod_sim_exp/trunk/sw/ModExp/.settings<br />+ /mod_sim_exp/trunk/sw/ModExp/.settings/org.eclipse.cdt.managedbuilder.core.prefs<br />+ /mod_sim_exp/trunk/sw/ModExp/Release<br />+ /mod_sim_exp/trunk/sw/ModExp/Release/ModExp.exe<br />+ /mod_sim_exp/trunk/sw/ModExp/Release/sim.txt<br />+ /mod_sim_exp/trunk/sw/ModExp/Release/src<br />+ /mod_sim_exp/trunk/sw/ModExp/src<br />+ /mod_sim_exp/trunk/sw/ModExp/src/ModExp.c<br />+ /mod_sim_exp/trunk/sw/ModMult<br />+ /mod_sim_exp/trunk/sw/ModMult/.cproject<br />+ /mod_sim_exp/trunk/sw/ModMult/.project<br />+ /mod_sim_exp/trunk/sw/ModMult/.settings<br />+ /mod_sim_exp/trunk/sw/ModMult/.settings/org.eclipse.cdt.managedbuilder.core.prefs<br />+ /mod_sim_exp/trunk/sw/ModMult/Release<br />+ /mod_sim_exp/trunk/sw/ModMult/Release/ModMult.exe<br />+ /mod_sim_exp/trunk/sw/ModMult/src<br />+ /mod_sim_exp/trunk/sw/ModMult/src/ModMult.c<br />JonasDCTue, 06 Nov 2012 20:22:15 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=29updated makefile for new pipeline sources
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=28
<div><strong>Rev 28 - JonasDC</strong> (1 file(s) modified)</div><div>updated makefile for new pipeline sources</div>~ /mod_sim_exp/trunk/sim/Makefile<br />JonasDCTue, 06 Nov 2012 19:43:40 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=28test input values for multiplier_tb
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=27
<div><strong>Rev 27 - JonasDC</strong> (1 file(s) modified)</div><div>test input values for multiplier_tb</div>+ /mod_sim_exp/trunk/sim/src/sim_mult_input.txt<br />JonasDCTue, 06 Nov 2012 19:43:05 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=27testbench for only the montgommery multiplier
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=26
<div><strong>Rev 26 - JonasDC</strong> (1 file(s) modified)</div><div>testbench for only the montgommery multiplier</div>+ /mod_sim_exp/trunk/bench/vhdl/multiplier_tb.vhd<br />JonasDCTue, 06 Nov 2012 19:42:16 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=26first version of new pipeline design. allows for more flexibility ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=25
<div><strong>Rev 25 - JonasDC</strong> (4 file(s) modified)</div><div>first version of new pipeline design. allows for more flexibility ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mont_multiplier.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_stage.vhd<br />JonasDCTue, 06 Nov 2012 19:41:36 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=25changed names of top-level module to mod_sim_exp_core
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=24
<div><strong>Rev 24 - JonasDC</strong> (8 file(s) modified)</div><div>changed names of top-level module to mod_sim_exp_core</div>~ /mod_sim_exp/trunk<br />+ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />- /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />JonasDCSat, 03 Nov 2012 10:43:00 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=24added descriptive comments
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=23
<div><strong>Rev 23 - JonasDC</strong> (2 file(s) modified)</div><div>added descriptive comments</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />JonasDCSat, 03 Nov 2012 09:31:50 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=23updated the systolic pipeline with descriptive signal names and comments
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=22
<div><strong>Rev 22 - JonasDC</strong> (2 file(s) modified)</div><div>updated the systolic pipeline with descriptive signal names and comments</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/systolic_pipeline.vhd<br />JonasDCWed, 31 Oct 2012 15:56:38 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=22changed x_i signal to xi
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=21
<div><strong>Rev 21 - JonasDC</strong> (3 file(s) modified)</div><div>changed x_i signal to xi</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/x_shift_reg.vhd<br />JonasDCTue, 30 Oct 2012 08:23:21 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=21