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mod_sim_exp
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https://opencores.org/websvn//websvn/listing?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&
Fri, 29 Mar 2024 02:07:50 +0100
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Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=93
<div><strong>Rev 93 - JonasDC</strong> (1 file(s) modified)</div><div>Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. ...</div>+ /mod_sim_exp/tags/Release_1.4<br />
JonasDC
Mon, 01 Jul 2013 12:12:40 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=93
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updated documentation with minor interrupt changes of AXI interface
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=92
<div><strong>Rev 92 - JonasDC</strong> (3 file(s) modified)</div><div>updated documentation with minor interrupt changes of AXI interface</div>~ /mod_sim_exp/trunk/doc/mod_sim_exp.pdf<br />~ /mod_sim_exp/trunk/doc/src/acknowl.tex<br />~ /mod_sim_exp/trunk/doc/src/axi_interface.tex<br />
JonasDC
Mon, 01 Jul 2013 12:07:54 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=92
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changed interrupt structure of AXI4-Lite interface. Now the interrupt has ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=91
<div><strong>Rev 91 - JonasDC</strong> (1 file(s) modified)</div><div>changed interrupt structure of AXI4-Lite interface. Now the interrupt has ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />
JonasDC
Sat, 29 Jun 2013 09:07:21 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=91
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reverted changes from previous revision, updated AXI version with testbench
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=90
<div><strong>Rev 90 - JonasDC</strong> (19 file(s) modified)</div><div>reverted changes from previous revision, updated AXI version with testbench</div>+ /mod_sim_exp/trunk/bench/vhdl/msec_axi_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />
JonasDC
Thu, 27 Jun 2013 18:31:38 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=90
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updated vhdl files so now different clock frequencies are posible ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=89
<div><strong>Rev 89 - JonasDC</strong> (17 file(s) modified)</div><div>updated vhdl files so now different clock frequencies are posible ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd<br />
JonasDC
Wed, 24 Apr 2013 20:19:10 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=89
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small update on documentation, changed fault in axi control_reg
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=88
<div><strong>Rev 88 - JonasDC</strong> (4 file(s) modified)</div><div>small update on documentation, changed fault in axi control_reg</div>~ /mod_sim_exp/trunk/doc/mod_sim_exp.pdf<br />~ /mod_sim_exp/trunk/doc/src/axi_interface.tex<br />~ /mod_sim_exp/trunk/doc/src/pictures/axi_control_reg.pdf<br />~ /mod_sim_exp/trunk/doc/src/pictures/latex_figs.vsd<br />
JonasDC
Thu, 18 Apr 2013 19:25:23 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=88
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updated documentation to version 1.4
core now supports the AXI4-Lite bus
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=87
<div><strong>Rev 87 - JonasDC</strong> (9 file(s) modified)</div><div>updated documentation to version 1.4<br />
core now supports the AXI4-Lite bus</div>~ /mod_sim_exp/trunk/doc/mod_sim_exp.pdf<br />~ /mod_sim_exp/trunk/doc/src/acknowl.tex<br />~ /mod_sim_exp/trunk/doc/src/architecture.tex<br />+ /mod_sim_exp/trunk/doc/src/axi_interface.tex<br />~ /mod_sim_exp/trunk/doc/src/mod_sim_exp.tex<br />+ /mod_sim_exp/trunk/doc/src/pictures/axi_control_reg.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/axi_mem.pdf<br />~ /mod_sim_exp/trunk/doc/src/pictures/latex_figs.vsd<br />~ /mod_sim_exp/trunk/doc/src/plb_interface.tex<br />
JonasDC
Thu, 18 Apr 2013 18:47:26 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=87
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update on previous
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=86
<div><strong>Rev 86 - JonasDC</strong> (1 file(s) modified)</div><div>update on previous</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />
JonasDC
Thu, 18 Apr 2013 18:45:24 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=86
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changed so that reset now also affects slave register
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=85
<div><strong>Rev 85 - JonasDC</strong> (1 file(s) modified)</div><div>changed so that reset now also affects slave register</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />
JonasDC
Thu, 18 Apr 2013 18:42:46 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=85
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AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=84
<div><strong>Rev 84 - JonasDC</strong> (9 file(s) modified)</div><div>AXI-Lite interface updated, now tested and verified on Xilinx FPGA<br />
renamed ...</div>/mod_sim_exp/trunk/bench/vhdl/axi_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/interface/axi/axi_lite_slave.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />
JonasDC
Wed, 17 Apr 2013 10:09:11 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=84
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now using values from mod_sim_exp_pkg instead of direct entity
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=83
<div><strong>Rev 83 - JonasDC</strong> (3 file(s) modified)</div><div>now using values from mod_sim_exp_pkg instead of direct entity</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />
JonasDC
Mon, 15 Apr 2013 09:18:25 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=83
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added first version of axi-lite interface and testbench for basic ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=82
<div><strong>Rev 82 - JonasDC</strong> (3 file(s) modified)</div><div>added first version of axi-lite interface and testbench for basic ...</div>+ /mod_sim_exp/trunk/bench/vhdl/axi_tb.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/axi<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/axi_lite_slave.vhd<br />
JonasDC
Fri, 29 Mar 2013 13:17:23 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=82
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updated files, now using the components of the mod_sim_exp_pkg instead ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=81
<div><strong>Rev 81 - JonasDC</strong> (2 file(s) modified)</div><div>updated files, now using the components of the mod_sim_exp_pkg instead ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />
JonasDC
Fri, 29 Mar 2013 13:13:14 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=81
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renamed to version 1.1 to follow the versioning system
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=80
<div><strong>Rev 80 - JonasDC</strong> (2 file(s) modified)</div><div>renamed to version 1.1 to follow the versioning system</div>- /mod_sim_exp/tags/Release_0.1.0<br />+ /mod_sim_exp/tags/Release_1.1<br />
JonasDC
Tue, 19 Mar 2013 19:22:21 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=80
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Tag for version 1.3 (with new ram style
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=79
<div><strong>Rev 79 - JonasDC</strong> (1 file(s) modified)</div><div>Tag for version 1.3 (with new ram style</div>+ /mod_sim_exp/tags/Release_1.3<br />
JonasDC
Tue, 19 Mar 2013 19:19:05 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=79
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updated documentation with new RAM style information
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=78
<div><strong>Rev 78 - JonasDC</strong> (8 file(s) modified)</div><div>updated documentation with new RAM style information</div>~ /mod_sim_exp/trunk/doc/mod_sim_exp.pdf<br />~ /mod_sim_exp/trunk/doc/src/acknowl.tex<br />~ /mod_sim_exp/trunk/doc/src/architecture.tex<br />~ /mod_sim_exp/trunk/doc/src/mod_sim_exp.tex<br />~ /mod_sim_exp/trunk/doc/src/pictures/latex_figs.vsd<br />~ /mod_sim_exp/trunk/doc/src/pictures/mod_sim_exp_core.pdf<br />~ /mod_sim_exp/trunk/doc/src/pictures/msec_memory.pdf<br />~ /mod_sim_exp/trunk/doc/src/plb_interface.tex<br />
JonasDC
Tue, 19 Mar 2013 19:17:21 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=78
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found fault in code, now synthesizes normally
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=77
<div><strong>Rev 77 - JonasDC</strong> (1 file(s) modified)</div><div>found fault in code, now synthesizes normally</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />
JonasDC
Wed, 13 Mar 2013 21:48:20 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=77
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testbench update
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=76
<div><strong>Rev 76 - JonasDC</strong> (1 file(s) modified)</div><div>testbench update</div>~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />
JonasDC
Mon, 11 Mar 2013 10:51:28 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=76
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made rw_address a vector of a fixed width
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=75
<div><strong>Rev 75 - JonasDC</strong> (3 file(s) modified)</div><div>made rw_address a vector of a fixed width</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />
JonasDC
Mon, 11 Mar 2013 10:50:34 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=75
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removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=74
<div><strong>Rev 74 - JonasDC</strong> (2 file(s) modified)</div><div>removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />
JonasDC
Fri, 08 Mar 2013 14:44:16 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2F&rev=74
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