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https://opencores.org/websvn//websvn/listing?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftags%2FRelease_1.1%2Frtl%2F&
Sat, 16 May 2026 17:08:26 +0100FeedCreator 1.7.2renamed to version 1.1 to follow the versioning system
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftags%2FRelease_1.1%2Frtl%2F&rev=80
<div><strong>Rev 80 - JonasDC</strong> (2 file(s) modified)</div><div>renamed to version 1.1 to follow the versioning system</div>- /mod_sim_exp/tags/Release_0.1.0<br />+ /mod_sim_exp/tags/Release_1.1<br />JonasDCTue, 19 Mar 2013 19:22:21 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftags%2FRelease_1.1%2Frtl%2F&rev=80First full stable version with documentation.
Includes flexible pipeline design, PLB ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftags%2FRelease_0.1.0%2Frtl%2F&rev=49
<div><strong>Rev 49 - JonasDC</strong> (1 file(s) modified)</div><div>First full stable version with documentation.<br />
Includes flexible pipeline design, PLB ...</div>+ /mod_sim_exp/tags/Release_0.1.0<br />JonasDCThu, 07 Feb 2013 18:50:35 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftags%2FRelease_0.1.0%2Frtl%2F&rev=49chance run_auto port or mod_sim_exp_core to exp_m
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=45
<div><strong>Rev 45 - JonasDC</strong> (3 file(s) modified)</div><div>chance run_auto port or mod_sim_exp_core to exp_m</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />JonasDCSat, 01 Dec 2012 13:56:05 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=45toplevel of the Modular Simultaneous Exponentiation IP core for the ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=44
<div><strong>Rev 44 - JonasDC</strong> (1 file(s) modified)</div><div>toplevel of the Modular Simultaneous Exponentiation IP core for the ...</div>+ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />JonasDCTue, 27 Nov 2012 20:29:09 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=44made the core parameters generics
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=43
<div><strong>Rev 43 - JonasDC</strong> (6 file(s) modified)</div><div>made the core parameters generics</div>~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/multiplier_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mont_mult1536.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />JonasDCTue, 27 Nov 2012 20:27:53 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=43corrected wrong library name for mod_sim_exp_pkg
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=42
<div><strong>Rev 42 - JonasDC</strong> (1 file(s) modified)</div><div>corrected wrong library name for mod_sim_exp_pkg</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />JonasDCWed, 21 Nov 2012 12:37:15 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=42removed deprecated files from version control
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=41
<div><strong>Rev 41 - JonasDC</strong> (8 file(s) modified)</div><div>removed deprecated files from version control</div>- /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/systolic_pipeline.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />JonasDCWed, 21 Nov 2012 12:33:22 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=41adjusted core instantiation to new core module name
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=40
<div><strong>Rev 40 - JonasDC</strong> (1 file(s) modified)</div><div>adjusted core instantiation to new core module name</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />JonasDCTue, 13 Nov 2012 08:31:43 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=40changed files to remove warnings from synthesis
last cell logic is ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=39
<div><strong>Rev 39 - JonasDC</strong> (8 file(s) modified)</div><div>changed files to remove warnings from synthesis<br />
last cell logic is ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/autorun_cntrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_last_cell_logic.vhd<br />JonasDCMon, 12 Nov 2012 21:18:13 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=39deprecated design files because of new pipeline structure, will be ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=38
<div><strong>Rev 38 - JonasDC</strong> (6 file(s) modified)</div><div>deprecated design files because of new pipeline structure, will be ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/systolic_pipeline.vhd<br />JonasDCMon, 12 Nov 2012 15:44:05 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=38changed names of some generics of the multiplier.
moved the parameters ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=37
<div><strong>Rev 37 - JonasDC</strong> (6 file(s) modified)</div><div>changed names of some generics of the multiplier.<br />
moved the parameters ...</div>~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_multiplier.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />JonasDCThu, 08 Nov 2012 18:46:15 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=37found bug in new pipeline structure, now working properly. (tested ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=36
<div><strong>Rev 36 - JonasDC</strong> (2 file(s) modified)</div><div>found bug in new pipeline structure, now working properly. (tested ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />JonasDCWed, 07 Nov 2012 22:36:19 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=36operand memory now supports custom operand widths, the internal memory ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=34
<div><strong>Rev 34 - JonasDC</strong> (3 file(s) modified)</div><div>operand memory now supports custom operand widths, the internal memory ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />JonasDCWed, 07 Nov 2012 19:01:11 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=34default pipeline changed to old version, there seems to be ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=33
<div><strong>Rev 33 - JonasDC</strong> (1 file(s) modified)</div><div>default pipeline changed to old version, there seems to be ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />JonasDCWed, 07 Nov 2012 16:11:50 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=33new systolic pipeline structure now has split pipeline support, tested ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=32
<div><strong>Rev 32 - JonasDC</strong> (3 file(s) modified)</div><div>new systolic pipeline structure now has split pipeline support, tested ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_multiplier.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />JonasDCWed, 07 Nov 2012 15:12:34 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=32put first cell logic of the pipeline in a separate ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=31
<div><strong>Rev 31 - JonasDC</strong> (4 file(s) modified)</div><div>put first cell logic of the pipeline in a separate ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_first_cell_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />JonasDCWed, 07 Nov 2012 10:01:55 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=31put last cell logic of the pipeline in a separate ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=30
<div><strong>Rev 30 - JonasDC</strong> (4 file(s) modified)</div><div>put last cell logic of the pipeline in a separate ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_last_cell_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />JonasDCWed, 07 Nov 2012 09:37:37 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=30first version of new pipeline design. allows for more flexibility ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=25
<div><strong>Rev 25 - JonasDC</strong> (4 file(s) modified)</div><div>first version of new pipeline design. allows for more flexibility ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mont_multiplier.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_stage.vhd<br />JonasDCTue, 06 Nov 2012 19:41:36 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=25changed names of top-level module to mod_sim_exp_core
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=24
<div><strong>Rev 24 - JonasDC</strong> (8 file(s) modified)</div><div>changed names of top-level module to mod_sim_exp_core</div>~ /mod_sim_exp/trunk<br />+ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />- /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />JonasDCSat, 03 Nov 2012 10:43:00 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=24added descriptive comments
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=23
<div><strong>Rev 23 - JonasDC</strong> (2 file(s) modified)</div><div>added descriptive comments</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />JonasDCSat, 03 Nov 2012 09:31:50 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2F&rev=23
