OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Error creating feed file, please check write permissions.
mod_sim_exp WebSVN RSS feed - mod_sim_exp https://opencores.org/websvn//websvn/listing?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftags%2FRelease_1.3%2F& Thu, 01 Dec 2022 19:30:21 +0100 FeedCreator 1.7.2 Tag for version 1.3 (with new ram style https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftags%2FRelease_1.3%2F&rev=79 <div><strong>Rev 79 - JonasDC</strong> (1 file(s) modified)</div><div>Tag for version 1.3 (with new ram style</div>+ /mod_sim_exp/tags/Release_1.3<br /> JonasDC Tue, 19 Mar 2013 19:19:05 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftags%2FRelease_1.3%2F&rev=79 updated documentation with new RAM style information https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=78 <div><strong>Rev 78 - JonasDC</strong> (8 file(s) modified)</div><div>updated documentation with new RAM style information</div>~ /mod_sim_exp/trunk/doc/mod_sim_exp.pdf<br />~ /mod_sim_exp/trunk/doc/src/acknowl.tex<br />~ /mod_sim_exp/trunk/doc/src/architecture.tex<br />~ /mod_sim_exp/trunk/doc/src/mod_sim_exp.tex<br />~ /mod_sim_exp/trunk/doc/src/pictures/latex_figs.vsd<br />~ /mod_sim_exp/trunk/doc/src/pictures/mod_sim_exp_core.pdf<br />~ /mod_sim_exp/trunk/doc/src/pictures/msec_memory.pdf<br />~ /mod_sim_exp/trunk/doc/src/plb_interface.tex<br /> JonasDC Tue, 19 Mar 2013 19:17:21 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=78 found fault in code, now synthesizes normally https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=77 <div><strong>Rev 77 - JonasDC</strong> (1 file(s) modified)</div><div>found fault in code, now synthesizes normally</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br /> JonasDC Wed, 13 Mar 2013 21:48:20 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=77 testbench update https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=76 <div><strong>Rev 76 - JonasDC</strong> (1 file(s) modified)</div><div>testbench update</div>~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br /> JonasDC Mon, 11 Mar 2013 10:51:28 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=76 made rw_address a vector of a fixed width https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=75 <div><strong>Rev 75 - JonasDC</strong> (3 file(s) modified)</div><div>made rw_address a vector of a fixed width</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br /> JonasDC Mon, 11 Mar 2013 10:50:34 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=75 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=74 <div><strong>Rev 74 - JonasDC</strong> (2 file(s) modified)</div><div>removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br /> JonasDC Fri, 08 Mar 2013 14:44:16 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=74 updated plb interface, mem_style and device generics added https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=73 <div><strong>Rev 73 - JonasDC</strong> (3 file(s) modified)</div><div>updated plb interface, mem_style and device generics added</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mont_mult1536.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br /> JonasDC Thu, 07 Mar 2013 15:32:03 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=73 deleted old resources https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=72 <div><strong>Rev 72 - JonasDC</strong> (8 file(s) modified)</div><div>deleted old resources</div>- /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm<br />- /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files<br />- /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm<br />- /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files<br />- /mod_sim_exp/trunk/syn/xilinx/ver010_msec_sum.html<br />- /mod_sim_exp/trunk/syn/xilinx/ver010_msec_syn.html<br />- /mod_sim_exp/trunk/syn/xilinx/ver011_msec_genRAM_sum.html<br />- /mod_sim_exp/trunk/syn/xilinx/ver011_msec_genRAM_syn.html<br /> JonasDC Wed, 06 Mar 2013 15:29:03 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=72 added synthesis report for altera and xilinx for the new ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=71 <div><strong>Rev 71 - JonasDC</strong> (34 file(s) modified)</div><div>added synthesis report for altera and xilinx for the new ...</div>+ /mod_sim_exp/trunk/syn/altera/log<br />+ /mod_sim_exp/trunk/syn/altera/log/fifo<br />+ /mod_sim_exp/trunk/syn/altera/log/fifo/generic_mes.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/fifo/generic_sum.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/mod_sim_exp_core<br />+ /mod_sim_exp/trunk/syn/altera/log/mod_sim_exp_core/ver011_msec_genRAM_res.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/mod_sim_exp_core/ver011_msec_genRAM_sum.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/operand_mem<br />+ /mod_sim_exp/trunk/syn/altera/log/operand_mem/asym_mes.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/operand_mem/asym_sum.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/operand_mem/generic_mes.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/operand_mem/generic_sum.htm<br />+ /mod_sim_exp/trunk/syn/xilinx/log<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/xil_prim_fifo_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/xil_prim_fifo_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/mod_sim_exp_core<br />+ /mod_sim_exp/trunk/syn/xilinx/log/mod_sim_exp_core/ver010_msec_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/mod_sim_exp_core/ver010_msec_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/mod_sim_exp_core/ver011_msec_genRAM_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/mod_sim_exp_core/ver011_msec_genRAM_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/asym_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/asym_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/generic_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/generic_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/xil_prim_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/xil_prim_syn.html<br />- /mod_sim_exp/trunk/syn/xilinx/operands_sp.pdf<br />+ /mod_sim_exp/trunk/syn/xilinx/src<br />+ /mod_sim_exp/trunk/syn/xilinx/src/operands_sp.xco<br />+ /mod_sim_exp/trunk/syn/xilinx/src/operand_dp.xco<br /> JonasDC Wed, 06 Mar 2013 15:27:23 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=71 updated testbench for use with new core parameters updated makefile, added ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=70 <div><strong>Rev 70 - JonasDC</strong> (5 file(s) modified)</div><div>updated testbench for use with new core parameters<br /> updated makefile, added ...</div>~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/sim<br />~ /mod_sim_exp/trunk/sim/Makefile<br />~ /mod_sim_exp/trunk/sim/mod_sim_exp.do<br />~ /mod_sim_exp/trunk/sim/out<br /> JonasDC Wed, 06 Mar 2013 15:21:18 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=70 big update, the mod_sim_exp core now has a selectable ram ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=69 <div><strong>Rev 69 - JonasDC</strong> (6 file(s) modified)</div><div>big update, the mod_sim_exp core now has a selectable ram ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />/mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br /> JonasDC Wed, 06 Mar 2013 15:19:04 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=69 added memory modules for modulus and operands for FPGA's that ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=67 <div><strong>Rev 67 - JonasDC</strong> (2 file(s) modified)</div><div>added memory modules for modulus and operands for FPGA's that ...</div>+ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br /> JonasDC Wed, 06 Mar 2013 12:16:29 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=67 added asymmetric ram structures to support a more performant ramstyle. defined ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=66 <div><strong>Rev 66 - JonasDC</strong> (4 file(s) modified)</div><div>added asymmetric ram structures to support a more performant ramstyle.<br /> defined ...</div>+ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd<br /> JonasDC Wed, 06 Mar 2013 12:05:05 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=66 updated plb interface, now modulus is selectable and, fifo depth ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=65 <div><strong>Rev 65 - JonasDC</strong> (4 file(s) modified)</div><div>updated plb interface, now modulus is selectable and, fifo depth ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br /> JonasDC Tue, 26 Feb 2013 20:15:46 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=65 added synthesis reports of xilinx and altera https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=64 <div><strong>Rev 64 - JonasDC</strong> (102 file(s) modified)</div><div>added synthesis reports of xilinx and altera</div>+ /mod_sim_exp/trunk/syn<br />+ /mod_sim_exp/trunk/syn/altera<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/1.htm<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/2.htm<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/css<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/css/base.css<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/css/jquery-ui.css<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/css/jquery.layout-latest.css<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/css/override.css<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/css/reset.css<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/afcq_bar_chart.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/afcq_closed_folder.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/afcq_generic_file.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/afcq_histogram.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/afcq_input_small.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/afcq_msg_critical_warning.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/afcq_msg_debug.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/afcq_msg_error.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/afcq_msg_extra_info.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/afcq_msg_info.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/afcq_msg_warning.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/afcq_opened_folder.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/afcq_question_mark.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/afcq_report_path.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/afcq_summary_table.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/afcq_table.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/afcq_timing_table.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/afcq_waveform.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/ui-bg_diagonals-thick_90_eeeeee_40x40.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/ui-bg_flat_15_cd0a0a_40x100.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/ui-bg_glass_50_3baae3_1x400.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/ui-bg_glass_80_d7ebf9_1x400.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/ui-bg_glass_100_e4f1fb_1x400.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/ui-bg_highlight-hard_70_000000_1x100.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/ui-bg_highlight-hard_100_f2f5f7_1x100.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/ui-bg_highlight-soft_25_ffef8f_1x100.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/ui-bg_highlight-soft_100_deedf7_1x100.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/ui-icons_2e83ff_256x240.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/ui-icons_3d80b3_256x240.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/ui-icons_72a7cf_256x240.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/ui-icons_2694e8_256x240.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/img/ui-icons_ffffff_256x240.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/js<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/js/jquery-ui.min.js<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/js/jquery.layout-latest.js<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files/js/jquery.min.js<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/1.htm<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/2.htm<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/css<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/css/base.css<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/css/jquery-ui.css<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/css/jquery.layout-latest.css<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/css/override.css<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/css/reset.css<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/afcq_bar_chart.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/afcq_closed_folder.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/afcq_generic_file.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/afcq_histogram.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/afcq_input_small.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/afcq_msg_critical_warning.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/afcq_msg_debug.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/afcq_msg_error.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/afcq_msg_extra_info.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/afcq_msg_info.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/afcq_msg_warning.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/afcq_opened_folder.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/afcq_question_mark.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/afcq_report_path.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/afcq_summary_table.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/afcq_table.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/afcq_timing_table.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/afcq_waveform.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/ui-bg_diagonals-thick_90_eeeeee_40x40.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/ui-bg_flat_15_cd0a0a_40x100.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/ui-bg_glass_50_3baae3_1x400.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/ui-bg_glass_80_d7ebf9_1x400.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/ui-bg_glass_100_e4f1fb_1x400.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/ui-bg_highlight-hard_70_000000_1x100.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/ui-bg_highlight-hard_100_f2f5f7_1x100.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/ui-bg_highlight-soft_25_ffef8f_1x100.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/ui-bg_highlight-soft_100_deedf7_1x100.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/ui-icons_2e83ff_256x240.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/ui-icons_3d80b3_256x240.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/ui-icons_72a7cf_256x240.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/ui-icons_2694e8_256x240.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/ui-icons_ffffff_256x240.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/js<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/js/jquery-ui.min.js<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/js/jquery.layout-latest.js<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/js/jquery.min.js<br />+ /mod_sim_exp/trunk/syn/xilinx<br />+ /mod_sim_exp/trunk/syn/xilinx/operands_sp.pdf<br />+ /mod_sim_exp/trunk/syn/xilinx/ver010_msec_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/ver010_msec_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/ver011_msec_genRAM_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/ver011_msec_genRAM_syn.html<br /> JonasDC Tue, 26 Feb 2013 14:49:12 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=64 now using a generic description of the ram for the ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=63 <div><strong>Rev 63 - JonasDC</strong> (5 file(s) modified)</div><div>now using a generic description of the ram for the ...</div>+ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem_gen.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br /> JonasDC Tue, 26 Feb 2013 14:45:30 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=63 not used anymore https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=62 <div><strong>Rev 62 - JonasDC</strong> (3 file(s) modified)</div><div>not used anymore</div>- /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_altera.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_xilinx.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_xilinx.vhd<br /> JonasDC Tue, 26 Feb 2013 12:01:21 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=62 updated comments, added optional altera constraint https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=61 <div><strong>Rev 61 - JonasDC</strong> (2 file(s) modified)</div><div>updated comments, added optional altera constraint</div>~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_generic.vhd<br /> JonasDC Tue, 26 Feb 2013 12:00:44 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=61 generic version of the fifo, not device specific anymore, uses ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=60 <div><strong>Rev 60 - JonasDC</strong> (3 file(s) modified)</div><div>generic version of the fifo, not device specific anymore, uses ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_generic.vhd<br /> JonasDC Sat, 23 Feb 2013 21:45:26 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=60 added templates that correctly infer RAM, for dual port en ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=59 <div><strong>Rev 59 - JonasDC</strong> (3 file(s) modified)</div><div>added templates that correctly infer RAM, for dual port en ...</div>+ /mod_sim_exp/trunk/rtl/vhdl/core/std_functions.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_generic.vhd<br /> JonasDC Sat, 23 Feb 2013 21:15:49 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=59
© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.