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mod_sim_exp WebSVN RSS feed - mod_sim_exp https://opencores.org/websvn//websvn/listing?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F& Fri, 24 Jun 2022 23:04:14 +0100 FeedCreator 1.7.2 Updated documentation to version 1.5 with dual-clock support https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=103 <div><strong>Rev 103 - JonasDC</strong> (6 file(s) modified)</div><div>Updated documentation to version 1.5 with dual-clock support</div>~ /mod_sim_exp/trunk/doc/mod_sim_exp.pdf<br />~ /mod_sim_exp/trunk/doc/src/acknowl.tex<br />~ /mod_sim_exp/trunk/doc/src/architecture.tex<br />~ /mod_sim_exp/trunk/doc/src/axi_interface.tex<br />~ /mod_sim_exp/trunk/doc/src/mod_sim_exp.tex<br />~ /mod_sim_exp/trunk/doc/src/plb_interface.tex<br /> JonasDC Wed, 21 Aug 2013 18:20:07 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=103 Added some extra information for the test generation software https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=102 <div><strong>Rev 102 - JonasDC</strong> (2 file(s) modified)</div><div>Added some extra information for the test generation software</div>+ /mod_sim_exp/trunk/sw/ModExp/README<br />+ /mod_sim_exp/trunk/sw/ModMult/README<br /> JonasDC Wed, 21 Aug 2013 18:14:37 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=102 added README file for simulation, minor update for Makefile clean ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=101 <div><strong>Rev 101 - JonasDC</strong> (2 file(s) modified)</div><div>added README file for simulation, minor update for Makefile clean ...</div>~ /mod_sim_exp/trunk/sim/Makefile<br />+ /mod_sim_exp/trunk/sim/README<br /> JonasDC Wed, 21 Aug 2013 14:09:42 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=101 changes in makefile, and fifo's are now also in ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=97 <div><strong>Rev 97 - JonasDC</strong> (2 file(s) modified)</div><div>changes in makefile, and fifo's are now also in ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br /> JonasDC Wed, 17 Jul 2013 13:45:38 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=97 minor makefile update https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=96 <div><strong>Rev 96 - JonasDC</strong> (1 file(s) modified)</div><div>minor makefile update</div>~ /mod_sim_exp/trunk/sim/Makefile<br /> JonasDC Tue, 16 Jul 2013 13:27:00 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=96 new control logic for the core, allow for greater frequencies ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=95 <div><strong>Rev 95 - JonasDC</strong> (2 file(s) modified)</div><div>new control logic for the core, allow for greater frequencies ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/autorun_cntrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br /> JonasDC Tue, 16 Jul 2013 13:25:35 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=95 BIG update: core now supports different clock speed for the ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=94 <div><strong>Rev 94 - JonasDC</strong> (38 file(s) modified)</div><div>BIG update: core now supports different clock speed for the ...</div>~ /mod_sim_exp/trunk/bench/vhdl/axi_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/msec_axi_tb.vhd<br />+ /mod_sim_exp/trunk/rtl/verilog<br />+ /mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc.v<br />+ /mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc_gray.v<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/clk_sync.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/pulse_cdc.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw5_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw5_syr.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw7_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw7_syr.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw5_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw5_syr.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw7_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw7_syr.html<br />~ /mod_sim_exp/trunk/syn/xilinx/src/operands_sp.xco<br />~ /mod_sim_exp/trunk/syn/xilinx/src/operand_dp.xco<br /> JonasDC Wed, 03 Jul 2013 17:20:18 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=94 updated documentation with minor interrupt changes of AXI interface https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=92 <div><strong>Rev 92 - JonasDC</strong> (3 file(s) modified)</div><div>updated documentation with minor interrupt changes of AXI interface</div>~ /mod_sim_exp/trunk/doc/mod_sim_exp.pdf<br />~ /mod_sim_exp/trunk/doc/src/acknowl.tex<br />~ /mod_sim_exp/trunk/doc/src/axi_interface.tex<br /> JonasDC Mon, 01 Jul 2013 12:07:54 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=92 changed interrupt structure of AXI4-Lite interface. Now the interrupt has ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=91 <div><strong>Rev 91 - JonasDC</strong> (1 file(s) modified)</div><div>changed interrupt structure of AXI4-Lite interface. Now the interrupt has ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br /> JonasDC Sat, 29 Jun 2013 09:07:21 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=91 reverted changes from previous revision, updated AXI version with testbench https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=90 <div><strong>Rev 90 - JonasDC</strong> (19 file(s) modified)</div><div>reverted changes from previous revision, updated AXI version with testbench</div>+ /mod_sim_exp/trunk/bench/vhdl/msec_axi_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br /> JonasDC Thu, 27 Jun 2013 18:31:38 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=90 updated vhdl files so now different clock frequencies are posible ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=89 <div><strong>Rev 89 - JonasDC</strong> (17 file(s) modified)</div><div>updated vhdl files so now different clock frequencies are posible ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd<br /> JonasDC Wed, 24 Apr 2013 20:19:10 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=89 small update on documentation, changed fault in axi control_reg https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=88 <div><strong>Rev 88 - JonasDC</strong> (4 file(s) modified)</div><div>small update on documentation, changed fault in axi control_reg</div>~ /mod_sim_exp/trunk/doc/mod_sim_exp.pdf<br />~ /mod_sim_exp/trunk/doc/src/axi_interface.tex<br />~ /mod_sim_exp/trunk/doc/src/pictures/axi_control_reg.pdf<br />~ /mod_sim_exp/trunk/doc/src/pictures/latex_figs.vsd<br /> JonasDC Thu, 18 Apr 2013 19:25:23 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=88 updated documentation to version 1.4 core now supports the AXI4-Lite bus https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=87 <div><strong>Rev 87 - JonasDC</strong> (9 file(s) modified)</div><div>updated documentation to version 1.4<br /> core now supports the AXI4-Lite bus</div>~ /mod_sim_exp/trunk/doc/mod_sim_exp.pdf<br />~ /mod_sim_exp/trunk/doc/src/acknowl.tex<br />~ /mod_sim_exp/trunk/doc/src/architecture.tex<br />+ /mod_sim_exp/trunk/doc/src/axi_interface.tex<br />~ /mod_sim_exp/trunk/doc/src/mod_sim_exp.tex<br />+ /mod_sim_exp/trunk/doc/src/pictures/axi_control_reg.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/axi_mem.pdf<br />~ /mod_sim_exp/trunk/doc/src/pictures/latex_figs.vsd<br />~ /mod_sim_exp/trunk/doc/src/plb_interface.tex<br /> JonasDC Thu, 18 Apr 2013 18:47:26 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=87 update on previous https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=86 <div><strong>Rev 86 - JonasDC</strong> (1 file(s) modified)</div><div>update on previous</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br /> JonasDC Thu, 18 Apr 2013 18:45:24 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=86 changed so that reset now also affects slave register https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=85 <div><strong>Rev 85 - JonasDC</strong> (1 file(s) modified)</div><div>changed so that reset now also affects slave register</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br /> JonasDC Thu, 18 Apr 2013 18:42:46 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=85 AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=84 <div><strong>Rev 84 - JonasDC</strong> (9 file(s) modified)</div><div>AXI-Lite interface updated, now tested and verified on Xilinx FPGA<br /> renamed ...</div>/mod_sim_exp/trunk/bench/vhdl/axi_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/interface/axi/axi_lite_slave.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br /> JonasDC Wed, 17 Apr 2013 10:09:11 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=84 now using values from mod_sim_exp_pkg instead of direct entity https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=83 <div><strong>Rev 83 - JonasDC</strong> (3 file(s) modified)</div><div>now using values from mod_sim_exp_pkg instead of direct entity</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br /> JonasDC Mon, 15 Apr 2013 09:18:25 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=83 added first version of axi-lite interface and testbench for basic ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=82 <div><strong>Rev 82 - JonasDC</strong> (3 file(s) modified)</div><div>added first version of axi-lite interface and testbench for basic ...</div>+ /mod_sim_exp/trunk/bench/vhdl/axi_tb.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/axi<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/axi_lite_slave.vhd<br /> JonasDC Fri, 29 Mar 2013 13:17:23 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=82 updated files, now using the components of the mod_sim_exp_pkg instead ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=81 <div><strong>Rev 81 - JonasDC</strong> (2 file(s) modified)</div><div>updated files, now using the components of the mod_sim_exp_pkg instead ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br /> JonasDC Fri, 29 Mar 2013 13:13:14 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=81 updated documentation with new RAM style information https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=78 <div><strong>Rev 78 - JonasDC</strong> (8 file(s) modified)</div><div>updated documentation with new RAM style information</div>~ /mod_sim_exp/trunk/doc/mod_sim_exp.pdf<br />~ /mod_sim_exp/trunk/doc/src/acknowl.tex<br />~ /mod_sim_exp/trunk/doc/src/architecture.tex<br />~ /mod_sim_exp/trunk/doc/src/mod_sim_exp.tex<br />~ /mod_sim_exp/trunk/doc/src/pictures/latex_figs.vsd<br />~ /mod_sim_exp/trunk/doc/src/pictures/mod_sim_exp_core.pdf<br />~ /mod_sim_exp/trunk/doc/src/pictures/msec_memory.pdf<br />~ /mod_sim_exp/trunk/doc/src/plb_interface.tex<br /> JonasDC Tue, 19 Mar 2013 19:17:21 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=78
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