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mod_sim_exp WebSVN RSS feed - mod_sim_exp https://opencores.org/websvn//websvn/listing?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F& Sat, 03 Jun 2023 01:54:19 +0100 FeedCreator 1.7.2 changed comments, file is now according to OC design rules https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=14 <div><strong>Rev 14 - JonasDC</strong> (1 file(s) modified)</div><div>changed comments, file is now according to OC design rules</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b.vhd<br /> JonasDC Tue, 23 Oct 2012 18:51:22 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=14 added some descriptive comments and added check for incorrect value's ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=13 <div><strong>Rev 13 - JonasDC</strong> (1 file(s) modified)</div><div>added some descriptive comments and added check for incorrect value's ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br /> JonasDC Tue, 23 Oct 2012 18:41:23 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=13 updated comments, file is now completely according to design rules https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=12 <div><strong>Rev 12 - JonasDC</strong> (1 file(s) modified)</div><div>updated comments, file is now completely according to design rules</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_block.vhd<br /> JonasDC Tue, 23 Oct 2012 18:38:14 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=12 simulation output folder https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=11 <div><strong>Rev 11 - JonasDC</strong> (1 file(s) modified)</div><div>simulation output folder</div>~ /mod_sim_exp/trunk/sim/out<br /> JonasDC Tue, 23 Oct 2012 16:22:17 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=11 changed signal input port names to correct name https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=10 <div><strong>Rev 10 - JonasDC</strong> (1 file(s) modified)</div><div>changed signal input port names to correct name</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br /> JonasDC Tue, 23 Oct 2012 13:42:32 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=10 added descriptive comments, and renamed input mux_result from cell_1b_adder to ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=9 <div><strong>Rev 9 - JonasDC</strong> (6 file(s) modified)</div><div>added descriptive comments, and renamed input mux_result from cell_1b_adder to ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_block.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_adder.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_mux.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br /> JonasDC Tue, 23 Oct 2012 13:41:23 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=9 added descriptive comments https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=8 <div><strong>Rev 8 - JonasDC</strong> (1 file(s) modified)</div><div>added descriptive comments</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_adder.vhd<br /> JonasDC Tue, 23 Oct 2012 11:30:44 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=8 Modified the architecture, no longer uses Xilinx primitive, instead generic ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=7 <div><strong>Rev 7 - JonasDC</strong> (1 file(s) modified)</div><div>Modified the architecture, no longer uses Xilinx primitive, instead generic ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/register_n.vhd<br /> JonasDC Tue, 23 Oct 2012 11:15:22 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=7 Modified the architecture, no longer uses Xilinx primitive, instead generic ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=6 <div><strong>Rev 6 - JonasDC</strong> (1 file(s) modified)</div><div>Modified the architecture, no longer uses Xilinx primitive, instead generic ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/register_1b.vhd<br /> JonasDC Tue, 23 Oct 2012 10:48:35 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=6 not needed on svn, is generated by testbench https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=5 <div><strong>Rev 5 - JonasDC</strong> (1 file(s) modified)</div><div>not needed on svn, is generated by testbench</div>- /mod_sim_exp/trunk/sim/out/sim_output.txt<br /> JonasDC Tue, 23 Oct 2012 10:39:08 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=5 Modified the architecture, no longer uses Xilinx primitive, instead generic ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=4 <div><strong>Rev 4 - JonasDC</strong> (1 file(s) modified)</div><div>Modified the architecture, no longer uses Xilinx primitive, instead generic ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/d_flip_flop.vhd<br /> JonasDC Tue, 23 Oct 2012 09:06:41 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=4 updated vhdl sources with new header according to OC design ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=3 <div><strong>Rev 3 - JonasDC</strong> (36 file(s) modified)</div><div>updated vhdl sources with new header according to OC design ...</div>~ /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_block.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/autorun_cntrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_adder.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_mux.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/d_flip_flop.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operands_sp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/register_1b.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/register_n.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_cell_block.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/std_logic_textio.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/stepping_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/systolic_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/x_shift_reg.vhd<br />+ /mod_sim_exp/trunk/sim<br />+ /mod_sim_exp/trunk/sim/Makefile<br />+ /mod_sim_exp/trunk/sim/mod_sim_exp.do<br />+ /mod_sim_exp/trunk/sim/out<br />+ /mod_sim_exp/trunk/sim/out/sim_output.txt<br />+ /mod_sim_exp/trunk/sim/src<br />+ /mod_sim_exp/trunk/sim/src/sim_input.txt<br /> JonasDC Mon, 22 Oct 2012 19:08:31 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=3 First version of VHDL source(working), still contains xilinx primitives and ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=2 <div><strong>Rev 2 - JonasDC</strong> (37 file(s) modified)</div><div>First version of VHDL source(working), still contains xilinx primitives and ...</div>+ /mod_sim_exp/trunk/bench<br />+ /mod_sim_exp/trunk/bench/vhdl<br />+ /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd<br />+ /mod_sim_exp/trunk/rtl<br />+ /mod_sim_exp/trunk/rtl/vhdl<br />+ /mod_sim_exp/trunk/rtl/vhdl/core<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/adder_block.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/autorun_cntrl.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_adder.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_mux.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/d_flip_flop.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operands_sp.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/register_1b.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/register_n.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/standard_cell_block.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/std_logic_textio.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/stepping_logic.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/systolic_pipeline.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/x_shift_reg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/plb<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mont_mult1536.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br /> JonasDC Thu, 18 Oct 2012 13:14:22 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=2 The project and the structure was created https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=1 <div><strong>Rev 1 - root</strong> (4 file(s) modified)</div><div>The project and the structure was created</div>+ /mod_sim_exp<br />+ /mod_sim_exp/branches<br />+ /mod_sim_exp/tags<br />+ /mod_sim_exp/trunk<br /> root Tue, 16 Oct 2012 13:45:02 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=1
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