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Thu, 28 Mar 2024 15:51:50 +0100FeedCreator 1.7.2new systolic pipeline structure now has split pipeline support, tested ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=32
<div><strong>Rev 32 - JonasDC</strong> (3 file(s) modified)</div><div>new systolic pipeline structure now has split pipeline support, tested ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_multiplier.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />JonasDCWed, 07 Nov 2012 15:12:34 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=32put first cell logic of the pipeline in a separate ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=31
<div><strong>Rev 31 - JonasDC</strong> (4 file(s) modified)</div><div>put first cell logic of the pipeline in a separate ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_first_cell_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />JonasDCWed, 07 Nov 2012 10:01:55 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=31put last cell logic of the pipeline in a separate ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=30
<div><strong>Rev 30 - JonasDC</strong> (4 file(s) modified)</div><div>put last cell logic of the pipeline in a separate ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_last_cell_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />JonasDCWed, 07 Nov 2012 09:37:37 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=30added software for generation of test input for the tesbenches
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=29
<div><strong>Rev 29 - JonasDC</strong> (21 file(s) modified)</div><div>added software for generation of test input for the tesbenches</div>+ /mod_sim_exp/trunk/sw<br />+ /mod_sim_exp/trunk/sw/ModExp<br />+ /mod_sim_exp/trunk/sw/ModExp/.cproject<br />+ /mod_sim_exp/trunk/sw/ModExp/.project<br />+ /mod_sim_exp/trunk/sw/ModExp/.settings<br />+ /mod_sim_exp/trunk/sw/ModExp/.settings/org.eclipse.cdt.managedbuilder.core.prefs<br />+ /mod_sim_exp/trunk/sw/ModExp/Release<br />+ /mod_sim_exp/trunk/sw/ModExp/Release/ModExp.exe<br />+ /mod_sim_exp/trunk/sw/ModExp/Release/sim.txt<br />+ /mod_sim_exp/trunk/sw/ModExp/Release/src<br />+ /mod_sim_exp/trunk/sw/ModExp/src<br />+ /mod_sim_exp/trunk/sw/ModExp/src/ModExp.c<br />+ /mod_sim_exp/trunk/sw/ModMult<br />+ /mod_sim_exp/trunk/sw/ModMult/.cproject<br />+ /mod_sim_exp/trunk/sw/ModMult/.project<br />+ /mod_sim_exp/trunk/sw/ModMult/.settings<br />+ /mod_sim_exp/trunk/sw/ModMult/.settings/org.eclipse.cdt.managedbuilder.core.prefs<br />+ /mod_sim_exp/trunk/sw/ModMult/Release<br />+ /mod_sim_exp/trunk/sw/ModMult/Release/ModMult.exe<br />+ /mod_sim_exp/trunk/sw/ModMult/src<br />+ /mod_sim_exp/trunk/sw/ModMult/src/ModMult.c<br />JonasDCTue, 06 Nov 2012 20:22:15 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=29updated makefile for new pipeline sources
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=28
<div><strong>Rev 28 - JonasDC</strong> (1 file(s) modified)</div><div>updated makefile for new pipeline sources</div>~ /mod_sim_exp/trunk/sim/Makefile<br />JonasDCTue, 06 Nov 2012 19:43:40 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=28test input values for multiplier_tb
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=27
<div><strong>Rev 27 - JonasDC</strong> (1 file(s) modified)</div><div>test input values for multiplier_tb</div>+ /mod_sim_exp/trunk/sim/src/sim_mult_input.txt<br />JonasDCTue, 06 Nov 2012 19:43:05 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=27testbench for only the montgommery multiplier
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=26
<div><strong>Rev 26 - JonasDC</strong> (1 file(s) modified)</div><div>testbench for only the montgommery multiplier</div>+ /mod_sim_exp/trunk/bench/vhdl/multiplier_tb.vhd<br />JonasDCTue, 06 Nov 2012 19:42:16 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=26first version of new pipeline design. allows for more flexibility ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=25
<div><strong>Rev 25 - JonasDC</strong> (4 file(s) modified)</div><div>first version of new pipeline design. allows for more flexibility ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mont_multiplier.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_stage.vhd<br />JonasDCTue, 06 Nov 2012 19:41:36 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=25changed names of top-level module to mod_sim_exp_core
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=24
<div><strong>Rev 24 - JonasDC</strong> (8 file(s) modified)</div><div>changed names of top-level module to mod_sim_exp_core</div>~ /mod_sim_exp/trunk<br />+ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />- /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />JonasDCSat, 03 Nov 2012 10:43:00 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=24added descriptive comments
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=23
<div><strong>Rev 23 - JonasDC</strong> (2 file(s) modified)</div><div>added descriptive comments</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />JonasDCSat, 03 Nov 2012 09:31:50 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=23updated the systolic pipeline with descriptive signal names and comments
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=22
<div><strong>Rev 22 - JonasDC</strong> (2 file(s) modified)</div><div>updated the systolic pipeline with descriptive signal names and comments</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/systolic_pipeline.vhd<br />JonasDCWed, 31 Oct 2012 15:56:38 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=22changed x_i signal to xi
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=21
<div><strong>Rev 21 - JonasDC</strong> (3 file(s) modified)</div><div>changed x_i signal to xi</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/x_shift_reg.vhd<br />JonasDCTue, 30 Oct 2012 08:23:21 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=21added comments, changed signal name of x_reg_i to x_reg.
File is ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=20
<div><strong>Rev 20 - JonasDC</strong> (2 file(s) modified)</div><div>added comments, changed signal name of x_reg_i to x_reg.<br />
File is ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/x_shift_reg.vhd<br />JonasDCTue, 30 Oct 2012 08:05:34 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=20updated files with descriptive comments
changed signal names and removed redundant ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=19
<div><strong>Rev 19 - JonasDC</strong> (3 file(s) modified)</div><div>updated files with descriptive comments<br />
changed signal names and removed redundant ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/stepping_logic.vhd<br />JonasDCThu, 25 Oct 2012 13:02:02 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=19updated stages with comments and renamed some signals for consistency
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=18
<div><strong>Rev 18 - JonasDC</strong> (4 file(s) modified)</div><div>updated stages with comments and renamed some signals for consistency</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />JonasDCWed, 24 Oct 2012 13:25:06 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=18updated files with descriptive comments and removed unnecessary signals in ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=17
<div><strong>Rev 17 - JonasDC</strong> (3 file(s) modified)</div><div>updated files with descriptive comments and removed unnecessary signals in ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_cell_block.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />JonasDCWed, 24 Oct 2012 08:25:16 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=17package with modified generic parameter for register_n
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=16
<div><strong>Rev 16 - JonasDC</strong> (1 file(s) modified)</div><div>package with modified generic parameter for register_n</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />JonasDCTue, 23 Oct 2012 19:20:35 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=16changed generic for register width from n to width for ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=15
<div><strong>Rev 15 - JonasDC</strong> (4 file(s) modified)</div><div>changed generic for register width from n to width for ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/register_n.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />JonasDCTue, 23 Oct 2012 19:15:55 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=15changed comments, file is now according to OC design rules
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=14
<div><strong>Rev 14 - JonasDC</strong> (1 file(s) modified)</div><div>changed comments, file is now according to OC design rules</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b.vhd<br />JonasDCTue, 23 Oct 2012 18:51:22 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=14added some descriptive comments and added check for incorrect value's ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=13
<div><strong>Rev 13 - JonasDC</strong> (1 file(s) modified)</div><div>added some descriptive comments and added check for incorrect value's ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br />JonasDCTue, 23 Oct 2012 18:41:23 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=13