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mod_sim_exp
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https://opencores.org/websvn//websvn/listing?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&
Thu, 28 Mar 2024 19:25:06 +0100
FeedCreator 1.7.2
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now using a generic description of the ram for the ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=63
<div><strong>Rev 63 - JonasDC</strong> (5 file(s) modified)</div><div>now using a generic description of the ram for the ...</div>+ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem_gen.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />
JonasDC
Tue, 26 Feb 2013 14:45:30 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=63
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not used anymore
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=62
<div><strong>Rev 62 - JonasDC</strong> (3 file(s) modified)</div><div>not used anymore</div>- /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_altera.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_xilinx.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_xilinx.vhd<br />
JonasDC
Tue, 26 Feb 2013 12:01:21 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=62
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updated comments, added optional altera constraint
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=61
<div><strong>Rev 61 - JonasDC</strong> (2 file(s) modified)</div><div>updated comments, added optional altera constraint</div>~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_generic.vhd<br />
JonasDC
Tue, 26 Feb 2013 12:00:44 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=61
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generic version of the fifo, not device specific anymore, uses ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=60
<div><strong>Rev 60 - JonasDC</strong> (3 file(s) modified)</div><div>generic version of the fifo, not device specific anymore, uses ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_generic.vhd<br />
JonasDC
Sat, 23 Feb 2013 21:45:26 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=60
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added templates that correctly infer RAM, for dual port en ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=59
<div><strong>Rev 59 - JonasDC</strong> (3 file(s) modified)</div><div>added templates that correctly infer RAM, for dual port en ...</div>+ /mod_sim_exp/trunk/rtl/vhdl/core/std_functions.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_generic.vhd<br />
JonasDC
Sat, 23 Feb 2013 21:15:49 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=59
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updated resource usage in comments
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=55
<div><strong>Rev 55 - JonasDC</strong> (1 file(s) modified)</div><div>updated resource usage in comments</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />
JonasDC
Tue, 19 Feb 2013 21:50:23 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=55
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generic fifo design: correctrly inferred by xilinx and altera
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=54
<div><strong>Rev 54 - JonasDC</strong> (1 file(s) modified)</div><div>generic fifo design: correctrly inferred by xilinx and altera</div>+ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />
JonasDC
Tue, 19 Feb 2013 21:37:39 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=54
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correctly inferred ram for altera dual port ram
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=53
<div><strong>Rev 53 - JonasDC</strong> (1 file(s) modified)</div><div>correctly inferred ram for altera dual port ram</div>+ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_altera.vhd<br />
JonasDC
Tue, 19 Feb 2013 14:59:11 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=53
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correct inferring of blockram, no additional resources.
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=52
<div><strong>Rev 52 - JonasDC</strong> (1 file(s) modified)</div><div>correct inferring of blockram, no additional resources.</div>~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_xilinx.vhd<br />
JonasDC
Tue, 19 Feb 2013 14:34:52 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=52
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true dual port ram for xilinx
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=51
<div><strong>Rev 51 - JonasDC</strong> (1 file(s) modified)</div><div>true dual port ram for xilinx</div>+ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_xilinx.vhd<br />
JonasDC
Tue, 19 Feb 2013 13:53:22 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=51
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added folder for ram descriptions
added experimental simple dual port ram ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=50
<div><strong>Rev 50 - JonasDC</strong> (2 file(s) modified)</div><div>added folder for ram descriptions<br />
added experimental simple dual port ram ...</div>+ /mod_sim_exp/trunk/rtl/vhdl/ram<br />+ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_xilinx.vhd<br />
JonasDC
Tue, 19 Feb 2013 13:51:30 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=50
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added documentation for the IP core.
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=47
<div><strong>Rev 47 - JonasDC</strong> (35 file(s) modified)</div><div>added documentation for the IP core.</div>+ /mod_sim_exp/trunk/doc<br />+ /mod_sim_exp/trunk/doc/mod_sim_exp.pdf<br />+ /mod_sim_exp/trunk/doc/src<br />+ /mod_sim_exp/trunk/doc/src/acknowl.tex<br />+ /mod_sim_exp/trunk/doc/src/architecture.tex<br />+ /mod_sim_exp/trunk/doc/src/cited.bib<br />+ /mod_sim_exp/trunk/doc/src/introduction.tex<br />+ /mod_sim_exp/trunk/doc/src/license.tex<br />+ /mod_sim_exp/trunk/doc/src/mod_sim_exp.tex<br />+ /mod_sim_exp/trunk/doc/src/mod_sim_exp_style.sty<br />+ /mod_sim_exp/trunk/doc/src/operation.tex<br />+ /mod_sim_exp/trunk/doc/src/performance.tex<br />+ /mod_sim_exp/trunk/doc/src/pictures<br />+ /mod_sim_exp/trunk/doc/src/pictures/block_diagram.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/latex_figs.vsd<br />+ /mod_sim_exp/trunk/doc/src/pictures/logos.jpg<br />+ /mod_sim_exp/trunk/doc/src/pictures/mod_sim_exp_core.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/msec_memory.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/mult_structure.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/OCsmall.png<br />+ /mod_sim_exp/trunk/doc/src/pictures/opencores.jpg<br />+ /mod_sim_exp/trunk/doc/src/pictures/pipeline_operation.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/plb_control_reg.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/plb_gie_reg.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/plb_ie_reg.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/plb_interface.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/plb_is_reg.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/Speedtest.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/sys_pipeline.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/sys_pipeline_notsplit.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/sys_stage.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/Virtex6_stagewidth.pdf<br />+ /mod_sim_exp/trunk/doc/src/plb_interface.tex<br />+ /mod_sim_exp/trunk/doc/src/Speedtest.xlsx<br />+ /mod_sim_exp/trunk/doc/src/tables.xlsx<br />
JonasDC
Sat, 01 Dec 2012 14:04:31 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=47
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chance run_auto port or mod_sim_exp_core to exp_m
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=46
<div><strong>Rev 46 - JonasDC</strong> (1 file(s) modified)</div><div>chance run_auto port or mod_sim_exp_core to exp_m</div>~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />
JonasDC
Sat, 01 Dec 2012 13:56:24 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=46
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chance run_auto port or mod_sim_exp_core to exp_m
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=45
<div><strong>Rev 45 - JonasDC</strong> (3 file(s) modified)</div><div>chance run_auto port or mod_sim_exp_core to exp_m</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />
JonasDC
Sat, 01 Dec 2012 13:56:05 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=45
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toplevel of the Modular Simultaneous Exponentiation IP core for the ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=44
<div><strong>Rev 44 - JonasDC</strong> (1 file(s) modified)</div><div>toplevel of the Modular Simultaneous Exponentiation IP core for the ...</div>+ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />
JonasDC
Tue, 27 Nov 2012 20:29:09 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=44
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made the core parameters generics
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=43
<div><strong>Rev 43 - JonasDC</strong> (6 file(s) modified)</div><div>made the core parameters generics</div>~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/multiplier_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mont_mult1536.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />
JonasDC
Tue, 27 Nov 2012 20:27:53 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=43
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corrected wrong library name for mod_sim_exp_pkg
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=42
<div><strong>Rev 42 - JonasDC</strong> (1 file(s) modified)</div><div>corrected wrong library name for mod_sim_exp_pkg</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />
JonasDC
Wed, 21 Nov 2012 12:37:15 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=42
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removed deprecated files from version control
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=41
<div><strong>Rev 41 - JonasDC</strong> (8 file(s) modified)</div><div>removed deprecated files from version control</div>- /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/systolic_pipeline.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />
JonasDC
Wed, 21 Nov 2012 12:33:22 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=41
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adjusted core instantiation to new core module name
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=40
<div><strong>Rev 40 - JonasDC</strong> (1 file(s) modified)</div><div>adjusted core instantiation to new core module name</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />
JonasDC
Tue, 13 Nov 2012 08:31:43 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=40
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changed files to remove warnings from synthesis
last cell logic is ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=39
<div><strong>Rev 39 - JonasDC</strong> (8 file(s) modified)</div><div>changed files to remove warnings from synthesis<br />
last cell logic is ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/autorun_cntrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_last_cell_logic.vhd<br />
JonasDC
Mon, 12 Nov 2012 21:18:13 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=39
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