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mod_sim_exp WebSVN RSS feed - mod_sim_exp https://opencores.org/websvn//websvn/listing?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F& Sun, 02 Oct 2022 03:38:25 +0100 FeedCreator 1.7.2 updated documentation with minor interrupt changes of AXI interface https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=92 <div><strong>Rev 92 - JonasDC</strong> (3 file(s) modified)</div><div>updated documentation with minor interrupt changes of AXI interface</div>~ /mod_sim_exp/trunk/doc/mod_sim_exp.pdf<br />~ /mod_sim_exp/trunk/doc/src/acknowl.tex<br />~ /mod_sim_exp/trunk/doc/src/axi_interface.tex<br /> JonasDC Mon, 01 Jul 2013 12:07:54 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=92 changed interrupt structure of AXI4-Lite interface. Now the interrupt has ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=91 <div><strong>Rev 91 - JonasDC</strong> (1 file(s) modified)</div><div>changed interrupt structure of AXI4-Lite interface. Now the interrupt has ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br /> JonasDC Sat, 29 Jun 2013 09:07:21 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=91 reverted changes from previous revision, updated AXI version with testbench https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=90 <div><strong>Rev 90 - JonasDC</strong> (19 file(s) modified)</div><div>reverted changes from previous revision, updated AXI version with testbench</div>+ /mod_sim_exp/trunk/bench/vhdl/msec_axi_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br /> JonasDC Thu, 27 Jun 2013 18:31:38 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=90 updated vhdl files so now different clock frequencies are posible ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=89 <div><strong>Rev 89 - JonasDC</strong> (17 file(s) modified)</div><div>updated vhdl files so now different clock frequencies are posible ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd<br /> JonasDC Wed, 24 Apr 2013 20:19:10 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=89 small update on documentation, changed fault in axi control_reg https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=88 <div><strong>Rev 88 - JonasDC</strong> (4 file(s) modified)</div><div>small update on documentation, changed fault in axi control_reg</div>~ /mod_sim_exp/trunk/doc/mod_sim_exp.pdf<br />~ /mod_sim_exp/trunk/doc/src/axi_interface.tex<br />~ /mod_sim_exp/trunk/doc/src/pictures/axi_control_reg.pdf<br />~ /mod_sim_exp/trunk/doc/src/pictures/latex_figs.vsd<br /> JonasDC Thu, 18 Apr 2013 19:25:23 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=88 updated documentation to version 1.4 core now supports the AXI4-Lite bus https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=87 <div><strong>Rev 87 - JonasDC</strong> (9 file(s) modified)</div><div>updated documentation to version 1.4<br /> core now supports the AXI4-Lite bus</div>~ /mod_sim_exp/trunk/doc/mod_sim_exp.pdf<br />~ /mod_sim_exp/trunk/doc/src/acknowl.tex<br />~ /mod_sim_exp/trunk/doc/src/architecture.tex<br />+ /mod_sim_exp/trunk/doc/src/axi_interface.tex<br />~ /mod_sim_exp/trunk/doc/src/mod_sim_exp.tex<br />+ /mod_sim_exp/trunk/doc/src/pictures/axi_control_reg.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/axi_mem.pdf<br />~ /mod_sim_exp/trunk/doc/src/pictures/latex_figs.vsd<br />~ /mod_sim_exp/trunk/doc/src/plb_interface.tex<br /> JonasDC Thu, 18 Apr 2013 18:47:26 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=87 update on previous https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=86 <div><strong>Rev 86 - JonasDC</strong> (1 file(s) modified)</div><div>update on previous</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br /> JonasDC Thu, 18 Apr 2013 18:45:24 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=86 changed so that reset now also affects slave register https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=85 <div><strong>Rev 85 - JonasDC</strong> (1 file(s) modified)</div><div>changed so that reset now also affects slave register</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br /> JonasDC Thu, 18 Apr 2013 18:42:46 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=85 AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=84 <div><strong>Rev 84 - JonasDC</strong> (9 file(s) modified)</div><div>AXI-Lite interface updated, now tested and verified on Xilinx FPGA<br /> renamed ...</div>/mod_sim_exp/trunk/bench/vhdl/axi_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/interface/axi/axi_lite_slave.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br /> JonasDC Wed, 17 Apr 2013 10:09:11 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=84 now using values from mod_sim_exp_pkg instead of direct entity https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=83 <div><strong>Rev 83 - JonasDC</strong> (3 file(s) modified)</div><div>now using values from mod_sim_exp_pkg instead of direct entity</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br /> JonasDC Mon, 15 Apr 2013 09:18:25 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=83 added first version of axi-lite interface and testbench for basic ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=82 <div><strong>Rev 82 - JonasDC</strong> (3 file(s) modified)</div><div>added first version of axi-lite interface and testbench for basic ...</div>+ /mod_sim_exp/trunk/bench/vhdl/axi_tb.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/axi<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/axi_lite_slave.vhd<br /> JonasDC Fri, 29 Mar 2013 13:17:23 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=82 updated files, now using the components of the mod_sim_exp_pkg instead ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=81 <div><strong>Rev 81 - JonasDC</strong> (2 file(s) modified)</div><div>updated files, now using the components of the mod_sim_exp_pkg instead ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br /> JonasDC Fri, 29 Mar 2013 13:13:14 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=81 updated documentation with new RAM style information https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=78 <div><strong>Rev 78 - JonasDC</strong> (8 file(s) modified)</div><div>updated documentation with new RAM style information</div>~ /mod_sim_exp/trunk/doc/mod_sim_exp.pdf<br />~ /mod_sim_exp/trunk/doc/src/acknowl.tex<br />~ /mod_sim_exp/trunk/doc/src/architecture.tex<br />~ /mod_sim_exp/trunk/doc/src/mod_sim_exp.tex<br />~ /mod_sim_exp/trunk/doc/src/pictures/latex_figs.vsd<br />~ /mod_sim_exp/trunk/doc/src/pictures/mod_sim_exp_core.pdf<br />~ /mod_sim_exp/trunk/doc/src/pictures/msec_memory.pdf<br />~ /mod_sim_exp/trunk/doc/src/plb_interface.tex<br /> JonasDC Tue, 19 Mar 2013 19:17:21 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=78 found fault in code, now synthesizes normally https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=77 <div><strong>Rev 77 - JonasDC</strong> (1 file(s) modified)</div><div>found fault in code, now synthesizes normally</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br /> JonasDC Wed, 13 Mar 2013 21:48:20 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=77 testbench update https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=76 <div><strong>Rev 76 - JonasDC</strong> (1 file(s) modified)</div><div>testbench update</div>~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br /> JonasDC Mon, 11 Mar 2013 10:51:28 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=76 made rw_address a vector of a fixed width https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=75 <div><strong>Rev 75 - JonasDC</strong> (3 file(s) modified)</div><div>made rw_address a vector of a fixed width</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br /> JonasDC Mon, 11 Mar 2013 10:50:34 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=75 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=74 <div><strong>Rev 74 - JonasDC</strong> (2 file(s) modified)</div><div>removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br /> JonasDC Fri, 08 Mar 2013 14:44:16 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=74 updated plb interface, mem_style and device generics added https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=73 <div><strong>Rev 73 - JonasDC</strong> (3 file(s) modified)</div><div>updated plb interface, mem_style and device generics added</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mont_mult1536.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br /> JonasDC Thu, 07 Mar 2013 15:32:03 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=73 deleted old resources https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=72 <div><strong>Rev 72 - JonasDC</strong> (8 file(s) modified)</div><div>deleted old resources</div>- /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm<br />- /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files<br />- /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm<br />- /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files<br />- /mod_sim_exp/trunk/syn/xilinx/ver010_msec_sum.html<br />- /mod_sim_exp/trunk/syn/xilinx/ver010_msec_syn.html<br />- /mod_sim_exp/trunk/syn/xilinx/ver011_msec_genRAM_sum.html<br />- /mod_sim_exp/trunk/syn/xilinx/ver011_msec_genRAM_syn.html<br /> JonasDC Wed, 06 Mar 2013 15:29:03 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=72 added synthesis report for altera and xilinx for the new ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=71 <div><strong>Rev 71 - JonasDC</strong> (34 file(s) modified)</div><div>added synthesis report for altera and xilinx for the new ...</div>+ /mod_sim_exp/trunk/syn/altera/log<br />+ /mod_sim_exp/trunk/syn/altera/log/fifo<br />+ /mod_sim_exp/trunk/syn/altera/log/fifo/generic_mes.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/fifo/generic_sum.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/mod_sim_exp_core<br />+ /mod_sim_exp/trunk/syn/altera/log/mod_sim_exp_core/ver011_msec_genRAM_res.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/mod_sim_exp_core/ver011_msec_genRAM_sum.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/operand_mem<br />+ /mod_sim_exp/trunk/syn/altera/log/operand_mem/asym_mes.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/operand_mem/asym_sum.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/operand_mem/generic_mes.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/operand_mem/generic_sum.htm<br />+ /mod_sim_exp/trunk/syn/xilinx/log<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/xil_prim_fifo_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/xil_prim_fifo_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/mod_sim_exp_core<br />+ /mod_sim_exp/trunk/syn/xilinx/log/mod_sim_exp_core/ver010_msec_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/mod_sim_exp_core/ver010_msec_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/mod_sim_exp_core/ver011_msec_genRAM_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/mod_sim_exp_core/ver011_msec_genRAM_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/asym_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/asym_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/generic_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/generic_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/xil_prim_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/xil_prim_syn.html<br />- /mod_sim_exp/trunk/syn/xilinx/operands_sp.pdf<br />+ /mod_sim_exp/trunk/syn/xilinx/src<br />+ /mod_sim_exp/trunk/syn/xilinx/src/operands_sp.xco<br />+ /mod_sim_exp/trunk/syn/xilinx/src/operand_dp.xco<br /> JonasDC Wed, 06 Mar 2013 15:27:23 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2F&rev=71
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