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mod_sim_exp WebSVN RSS feed - mod_sim_exp https://opencores.org/websvn//websvn/listing?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F& Sun, 02 Oct 2022 03:56:26 +0100 FeedCreator 1.7.2 reverted changes from previous revision, updated AXI version with testbench https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=90 <div><strong>Rev 90 - JonasDC</strong> (19 file(s) modified)</div><div>reverted changes from previous revision, updated AXI version with testbench</div>+ /mod_sim_exp/trunk/bench/vhdl/msec_axi_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br /> JonasDC Thu, 27 Jun 2013 18:31:38 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=90 AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=84 <div><strong>Rev 84 - JonasDC</strong> (9 file(s) modified)</div><div>AXI-Lite interface updated, now tested and verified on Xilinx FPGA<br /> renamed ...</div>/mod_sim_exp/trunk/bench/vhdl/axi_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/interface/axi/axi_lite_slave.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br /> JonasDC Wed, 17 Apr 2013 10:09:11 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=84 added first version of axi-lite interface and testbench for basic ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=82 <div><strong>Rev 82 - JonasDC</strong> (3 file(s) modified)</div><div>added first version of axi-lite interface and testbench for basic ...</div>+ /mod_sim_exp/trunk/bench/vhdl/axi_tb.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/axi<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/axi_lite_slave.vhd<br /> JonasDC Fri, 29 Mar 2013 13:17:23 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=82 testbench update https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=76 <div><strong>Rev 76 - JonasDC</strong> (1 file(s) modified)</div><div>testbench update</div>~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br /> JonasDC Mon, 11 Mar 2013 10:51:28 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=76 updated testbench for use with new core parameters updated makefile, added ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=70 <div><strong>Rev 70 - JonasDC</strong> (5 file(s) modified)</div><div>updated testbench for use with new core parameters<br /> updated makefile, added ...</div>~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/sim<br />~ /mod_sim_exp/trunk/sim/Makefile<br />~ /mod_sim_exp/trunk/sim/mod_sim_exp.do<br />~ /mod_sim_exp/trunk/sim/out<br /> JonasDC Wed, 06 Mar 2013 15:21:18 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=70 chance run_auto port or mod_sim_exp_core to exp_m https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=46 <div><strong>Rev 46 - JonasDC</strong> (1 file(s) modified)</div><div>chance run_auto port or mod_sim_exp_core to exp_m</div>~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br /> JonasDC Sat, 01 Dec 2012 13:56:24 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=46 made the core parameters generics https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=43 <div><strong>Rev 43 - JonasDC</strong> (6 file(s) modified)</div><div>made the core parameters generics</div>~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/multiplier_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mont_mult1536.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br /> JonasDC Tue, 27 Nov 2012 20:27:53 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=43 changed names of some generics of the multiplier. moved the parameters ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=37 <div><strong>Rev 37 - JonasDC</strong> (6 file(s) modified)</div><div>changed names of some generics of the multiplier.<br /> moved the parameters ...</div>~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_multiplier.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br /> JonasDC Thu, 08 Nov 2012 18:46:15 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=37 testbench for only the montgommery multiplier https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=26 <div><strong>Rev 26 - JonasDC</strong> (1 file(s) modified)</div><div>testbench for only the montgommery multiplier</div>+ /mod_sim_exp/trunk/bench/vhdl/multiplier_tb.vhd<br /> JonasDC Tue, 06 Nov 2012 19:42:16 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=26 changed names of top-level module to mod_sim_exp_core https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=24 <div><strong>Rev 24 - JonasDC</strong> (8 file(s) modified)</div><div>changed names of top-level module to mod_sim_exp_core</div>~ /mod_sim_exp/trunk<br />+ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />- /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br /> JonasDC Sat, 03 Nov 2012 10:43:00 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=24 updated vhdl sources with new header according to OC design ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=3 <div><strong>Rev 3 - JonasDC</strong> (36 file(s) modified)</div><div>updated vhdl sources with new header according to OC design ...</div>~ /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_block.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/autorun_cntrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_adder.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_mux.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/d_flip_flop.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operands_sp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/register_1b.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/register_n.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_cell_block.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/std_logic_textio.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/stepping_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/systolic_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/x_shift_reg.vhd<br />+ /mod_sim_exp/trunk/sim<br />+ /mod_sim_exp/trunk/sim/Makefile<br />+ /mod_sim_exp/trunk/sim/mod_sim_exp.do<br />+ /mod_sim_exp/trunk/sim/out<br />+ /mod_sim_exp/trunk/sim/out/sim_output.txt<br />+ /mod_sim_exp/trunk/sim/src<br />+ /mod_sim_exp/trunk/sim/src/sim_input.txt<br /> JonasDC Mon, 22 Oct 2012 19:08:31 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=3 First version of VHDL source(working), still contains xilinx primitives and ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=2 <div><strong>Rev 2 - JonasDC</strong> (37 file(s) modified)</div><div>First version of VHDL source(working), still contains xilinx primitives and ...</div>+ /mod_sim_exp/trunk/bench<br />+ /mod_sim_exp/trunk/bench/vhdl<br />+ /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd<br />+ /mod_sim_exp/trunk/rtl<br />+ /mod_sim_exp/trunk/rtl/vhdl<br />+ /mod_sim_exp/trunk/rtl/vhdl/core<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/adder_block.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/autorun_cntrl.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_adder.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_mux.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/d_flip_flop.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operands_sp.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/register_1b.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/register_n.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/standard_cell_block.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/std_logic_textio.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/stepping_logic.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/systolic_pipeline.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/x_shift_reg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/plb<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mont_mult1536.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br /> JonasDC Thu, 18 Oct 2012 13:14:22 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fbench%2F&rev=2
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