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mod_sim_exp WebSVN RSS feed - mod_sim_exp https://opencores.org/websvn//websvn/listing?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fdoc%2Fsrc%2F& Wed, 28 Sep 2022 02:39:36 +0100 FeedCreator 1.7.2 small update on documentation, changed fault in axi control_reg https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fdoc%2Fsrc%2F&rev=88 <div><strong>Rev 88 - JonasDC</strong> (4 file(s) modified)</div><div>small update on documentation, changed fault in axi control_reg</div>~ /mod_sim_exp/trunk/doc/mod_sim_exp.pdf<br />~ /mod_sim_exp/trunk/doc/src/axi_interface.tex<br />~ /mod_sim_exp/trunk/doc/src/pictures/axi_control_reg.pdf<br />~ /mod_sim_exp/trunk/doc/src/pictures/latex_figs.vsd<br /> JonasDC Thu, 18 Apr 2013 19:25:23 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fdoc%2Fsrc%2F&rev=88 updated documentation to version 1.4 core now supports the AXI4-Lite bus https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fdoc%2Fsrc%2F&rev=87 <div><strong>Rev 87 - JonasDC</strong> (9 file(s) modified)</div><div>updated documentation to version 1.4<br /> core now supports the AXI4-Lite bus</div>~ /mod_sim_exp/trunk/doc/mod_sim_exp.pdf<br />~ /mod_sim_exp/trunk/doc/src/acknowl.tex<br />~ /mod_sim_exp/trunk/doc/src/architecture.tex<br />+ /mod_sim_exp/trunk/doc/src/axi_interface.tex<br />~ /mod_sim_exp/trunk/doc/src/mod_sim_exp.tex<br />+ /mod_sim_exp/trunk/doc/src/pictures/axi_control_reg.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/axi_mem.pdf<br />~ /mod_sim_exp/trunk/doc/src/pictures/latex_figs.vsd<br />~ /mod_sim_exp/trunk/doc/src/plb_interface.tex<br /> JonasDC Thu, 18 Apr 2013 18:47:26 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fdoc%2Fsrc%2F&rev=87 updated documentation with new RAM style information https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fdoc%2Fsrc%2F&rev=78 <div><strong>Rev 78 - JonasDC</strong> (8 file(s) modified)</div><div>updated documentation with new RAM style information</div>~ /mod_sim_exp/trunk/doc/mod_sim_exp.pdf<br />~ /mod_sim_exp/trunk/doc/src/acknowl.tex<br />~ /mod_sim_exp/trunk/doc/src/architecture.tex<br />~ /mod_sim_exp/trunk/doc/src/mod_sim_exp.tex<br />~ /mod_sim_exp/trunk/doc/src/pictures/latex_figs.vsd<br />~ /mod_sim_exp/trunk/doc/src/pictures/mod_sim_exp_core.pdf<br />~ /mod_sim_exp/trunk/doc/src/pictures/msec_memory.pdf<br />~ /mod_sim_exp/trunk/doc/src/plb_interface.tex<br /> JonasDC Tue, 19 Mar 2013 19:17:21 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fdoc%2Fsrc%2F&rev=78 added documentation for the IP core. https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fdoc%2Fsrc%2F&rev=47 <div><strong>Rev 47 - JonasDC</strong> (35 file(s) modified)</div><div>added documentation for the IP core.</div>+ /mod_sim_exp/trunk/doc<br />+ /mod_sim_exp/trunk/doc/mod_sim_exp.pdf<br />+ /mod_sim_exp/trunk/doc/src<br />+ /mod_sim_exp/trunk/doc/src/acknowl.tex<br />+ /mod_sim_exp/trunk/doc/src/architecture.tex<br />+ /mod_sim_exp/trunk/doc/src/cited.bib<br />+ /mod_sim_exp/trunk/doc/src/introduction.tex<br />+ /mod_sim_exp/trunk/doc/src/license.tex<br />+ /mod_sim_exp/trunk/doc/src/mod_sim_exp.tex<br />+ /mod_sim_exp/trunk/doc/src/mod_sim_exp_style.sty<br />+ /mod_sim_exp/trunk/doc/src/operation.tex<br />+ /mod_sim_exp/trunk/doc/src/performance.tex<br />+ /mod_sim_exp/trunk/doc/src/pictures<br />+ /mod_sim_exp/trunk/doc/src/pictures/block_diagram.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/latex_figs.vsd<br />+ /mod_sim_exp/trunk/doc/src/pictures/logos.jpg<br />+ /mod_sim_exp/trunk/doc/src/pictures/mod_sim_exp_core.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/msec_memory.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/mult_structure.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/OCsmall.png<br />+ /mod_sim_exp/trunk/doc/src/pictures/opencores.jpg<br />+ /mod_sim_exp/trunk/doc/src/pictures/pipeline_operation.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/plb_control_reg.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/plb_gie_reg.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/plb_ie_reg.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/plb_interface.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/plb_is_reg.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/Speedtest.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/sys_pipeline.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/sys_pipeline_notsplit.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/sys_stage.pdf<br />+ /mod_sim_exp/trunk/doc/src/pictures/Virtex6_stagewidth.pdf<br />+ /mod_sim_exp/trunk/doc/src/plb_interface.tex<br />+ /mod_sim_exp/trunk/doc/src/Speedtest.xlsx<br />+ /mod_sim_exp/trunk/doc/src/tables.xlsx<br /> JonasDC Sat, 01 Dec 2012 14:04:31 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fdoc%2Fsrc%2F&rev=47
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