URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Error creating feed file, please check write permissions.
mod_sim_exp
WebSVN RSS feed - mod_sim_exp
https://opencores.org/websvn//websvn/listing?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&
Thu, 28 Mar 2024 17:50:24 +0100
FeedCreator 1.7.2
-
first version of new pipeline design. allows for more flexibility ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=25
<div><strong>Rev 25 - JonasDC</strong> (4 file(s) modified)</div><div>first version of new pipeline design. allows for more flexibility ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mont_multiplier.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_stage.vhd<br />
JonasDC
Tue, 06 Nov 2012 19:41:36 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=25
-
changed names of top-level module to mod_sim_exp_core
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=24
<div><strong>Rev 24 - JonasDC</strong> (8 file(s) modified)</div><div>changed names of top-level module to mod_sim_exp_core</div>~ /mod_sim_exp/trunk<br />+ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />- /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />
JonasDC
Sat, 03 Nov 2012 10:43:00 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=24
-
added descriptive comments
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=23
<div><strong>Rev 23 - JonasDC</strong> (2 file(s) modified)</div><div>added descriptive comments</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />
JonasDC
Sat, 03 Nov 2012 09:31:50 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=23
-
updated the systolic pipeline with descriptive signal names and comments
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=22
<div><strong>Rev 22 - JonasDC</strong> (2 file(s) modified)</div><div>updated the systolic pipeline with descriptive signal names and comments</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/systolic_pipeline.vhd<br />
JonasDC
Wed, 31 Oct 2012 15:56:38 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=22
-
changed x_i signal to xi
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=21
<div><strong>Rev 21 - JonasDC</strong> (3 file(s) modified)</div><div>changed x_i signal to xi</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/x_shift_reg.vhd<br />
JonasDC
Tue, 30 Oct 2012 08:23:21 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=21
-
added comments, changed signal name of x_reg_i to x_reg.
File is ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=20
<div><strong>Rev 20 - JonasDC</strong> (2 file(s) modified)</div><div>added comments, changed signal name of x_reg_i to x_reg.<br />
File is ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/x_shift_reg.vhd<br />
JonasDC
Tue, 30 Oct 2012 08:05:34 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=20
-
updated files with descriptive comments
changed signal names and removed redundant ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=19
<div><strong>Rev 19 - JonasDC</strong> (3 file(s) modified)</div><div>updated files with descriptive comments<br />
changed signal names and removed redundant ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/stepping_logic.vhd<br />
JonasDC
Thu, 25 Oct 2012 13:02:02 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=19
-
updated stages with comments and renamed some signals for consistency
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=18
<div><strong>Rev 18 - JonasDC</strong> (4 file(s) modified)</div><div>updated stages with comments and renamed some signals for consistency</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />
JonasDC
Wed, 24 Oct 2012 13:25:06 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=18
-
updated files with descriptive comments and removed unnecessary signals in ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=17
<div><strong>Rev 17 - JonasDC</strong> (3 file(s) modified)</div><div>updated files with descriptive comments and removed unnecessary signals in ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_cell_block.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />
JonasDC
Wed, 24 Oct 2012 08:25:16 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=17
-
package with modified generic parameter for register_n
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=16
<div><strong>Rev 16 - JonasDC</strong> (1 file(s) modified)</div><div>package with modified generic parameter for register_n</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />
JonasDC
Tue, 23 Oct 2012 19:20:35 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=16
-
changed generic for register width from n to width for ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=15
<div><strong>Rev 15 - JonasDC</strong> (4 file(s) modified)</div><div>changed generic for register width from n to width for ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/register_n.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />
JonasDC
Tue, 23 Oct 2012 19:15:55 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=15
-
changed comments, file is now according to OC design rules
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=14
<div><strong>Rev 14 - JonasDC</strong> (1 file(s) modified)</div><div>changed comments, file is now according to OC design rules</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b.vhd<br />
JonasDC
Tue, 23 Oct 2012 18:51:22 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=14
-
added some descriptive comments and added check for incorrect value's ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=13
<div><strong>Rev 13 - JonasDC</strong> (1 file(s) modified)</div><div>added some descriptive comments and added check for incorrect value's ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br />
JonasDC
Tue, 23 Oct 2012 18:41:23 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=13
-
updated comments, file is now completely according to design rules
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=12
<div><strong>Rev 12 - JonasDC</strong> (1 file(s) modified)</div><div>updated comments, file is now completely according to design rules</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_block.vhd<br />
JonasDC
Tue, 23 Oct 2012 18:38:14 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=12
-
changed signal input port names to correct name
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=10
<div><strong>Rev 10 - JonasDC</strong> (1 file(s) modified)</div><div>changed signal input port names to correct name</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />
JonasDC
Tue, 23 Oct 2012 13:42:32 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=10
-
added descriptive comments, and renamed input mux_result from cell_1b_adder to ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=9
<div><strong>Rev 9 - JonasDC</strong> (6 file(s) modified)</div><div>added descriptive comments, and renamed input mux_result from cell_1b_adder to ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_block.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_adder.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_mux.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />
JonasDC
Tue, 23 Oct 2012 13:41:23 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=9
-
added descriptive comments
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=8
<div><strong>Rev 8 - JonasDC</strong> (1 file(s) modified)</div><div>added descriptive comments</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_adder.vhd<br />
JonasDC
Tue, 23 Oct 2012 11:30:44 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=8
-
Modified the architecture, no longer uses Xilinx primitive, instead generic ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=7
<div><strong>Rev 7 - JonasDC</strong> (1 file(s) modified)</div><div>Modified the architecture, no longer uses Xilinx primitive, instead generic ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/register_n.vhd<br />
JonasDC
Tue, 23 Oct 2012 11:15:22 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=7
-
Modified the architecture, no longer uses Xilinx primitive, instead generic ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=6
<div><strong>Rev 6 - JonasDC</strong> (1 file(s) modified)</div><div>Modified the architecture, no longer uses Xilinx primitive, instead generic ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/register_1b.vhd<br />
JonasDC
Tue, 23 Oct 2012 10:48:35 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=6
-
Modified the architecture, no longer uses Xilinx primitive, instead generic ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=4
<div><strong>Rev 4 - JonasDC</strong> (1 file(s) modified)</div><div>Modified the architecture, no longer uses Xilinx primitive, instead generic ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/d_flip_flop.vhd<br />
JonasDC
Tue, 23 Oct 2012 09:06:41 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2F&rev=4
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.