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mod_sim_exp WebSVN RSS feed - mod_sim_exp https://opencores.org/websvn//websvn/listing?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F& Thu, 02 Feb 2023 08:51:50 +0100 FeedCreator 1.7.2 changed files to remove warnings from synthesis last cell logic is ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=39 <div><strong>Rev 39 - JonasDC</strong> (8 file(s) modified)</div><div>changed files to remove warnings from synthesis<br /> last cell logic is ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/autorun_cntrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_last_cell_logic.vhd<br /> JonasDC Mon, 12 Nov 2012 21:18:13 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=39 deprecated design files because of new pipeline structure, will be ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=38 <div><strong>Rev 38 - JonasDC</strong> (6 file(s) modified)</div><div>deprecated design files because of new pipeline structure, will be ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/systolic_pipeline.vhd<br /> JonasDC Mon, 12 Nov 2012 15:44:05 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=38 changed names of some generics of the multiplier. moved the parameters ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=37 <div><strong>Rev 37 - JonasDC</strong> (6 file(s) modified)</div><div>changed names of some generics of the multiplier.<br /> moved the parameters ...</div>~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_multiplier.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br /> JonasDC Thu, 08 Nov 2012 18:46:15 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=37 found bug in new pipeline structure, now working properly. (tested ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=36 <div><strong>Rev 36 - JonasDC</strong> (2 file(s) modified)</div><div>found bug in new pipeline structure, now working properly. (tested ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br /> JonasDC Wed, 07 Nov 2012 22:36:19 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=36 operand memory now supports custom operand widths, the internal memory ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=34 <div><strong>Rev 34 - JonasDC</strong> (3 file(s) modified)</div><div>operand memory now supports custom operand widths, the internal memory ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br /> JonasDC Wed, 07 Nov 2012 19:01:11 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=34 default pipeline changed to old version, there seems to be ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=33 <div><strong>Rev 33 - JonasDC</strong> (1 file(s) modified)</div><div>default pipeline changed to old version, there seems to be ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br /> JonasDC Wed, 07 Nov 2012 16:11:50 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=33 new systolic pipeline structure now has split pipeline support, tested ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=32 <div><strong>Rev 32 - JonasDC</strong> (3 file(s) modified)</div><div>new systolic pipeline structure now has split pipeline support, tested ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_multiplier.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br /> JonasDC Wed, 07 Nov 2012 15:12:34 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=32 put first cell logic of the pipeline in a separate ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=31 <div><strong>Rev 31 - JonasDC</strong> (4 file(s) modified)</div><div>put first cell logic of the pipeline in a separate ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_first_cell_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br /> JonasDC Wed, 07 Nov 2012 10:01:55 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=31 put last cell logic of the pipeline in a separate ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=30 <div><strong>Rev 30 - JonasDC</strong> (4 file(s) modified)</div><div>put last cell logic of the pipeline in a separate ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_last_cell_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br /> JonasDC Wed, 07 Nov 2012 09:37:37 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=30 first version of new pipeline design. allows for more flexibility ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=25 <div><strong>Rev 25 - JonasDC</strong> (4 file(s) modified)</div><div>first version of new pipeline design. allows for more flexibility ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mont_multiplier.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_stage.vhd<br /> JonasDC Tue, 06 Nov 2012 19:41:36 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=25 changed names of top-level module to mod_sim_exp_core https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=24 <div><strong>Rev 24 - JonasDC</strong> (8 file(s) modified)</div><div>changed names of top-level module to mod_sim_exp_core</div>~ /mod_sim_exp/trunk<br />+ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />- /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br /> JonasDC Sat, 03 Nov 2012 10:43:00 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=24 added descriptive comments https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=23 <div><strong>Rev 23 - JonasDC</strong> (2 file(s) modified)</div><div>added descriptive comments</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br /> JonasDC Sat, 03 Nov 2012 09:31:50 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=23 updated the systolic pipeline with descriptive signal names and comments https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=22 <div><strong>Rev 22 - JonasDC</strong> (2 file(s) modified)</div><div>updated the systolic pipeline with descriptive signal names and comments</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/systolic_pipeline.vhd<br /> JonasDC Wed, 31 Oct 2012 15:56:38 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=22 changed x_i signal to xi https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=21 <div><strong>Rev 21 - JonasDC</strong> (3 file(s) modified)</div><div>changed x_i signal to xi</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/x_shift_reg.vhd<br /> JonasDC Tue, 30 Oct 2012 08:23:21 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=21 added comments, changed signal name of x_reg_i to x_reg. File is ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=20 <div><strong>Rev 20 - JonasDC</strong> (2 file(s) modified)</div><div>added comments, changed signal name of x_reg_i to x_reg.<br /> File is ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/x_shift_reg.vhd<br /> JonasDC Tue, 30 Oct 2012 08:05:34 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=20 updated files with descriptive comments changed signal names and removed redundant ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=19 <div><strong>Rev 19 - JonasDC</strong> (3 file(s) modified)</div><div>updated files with descriptive comments<br /> changed signal names and removed redundant ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/stepping_logic.vhd<br /> JonasDC Thu, 25 Oct 2012 13:02:02 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=19 updated stages with comments and renamed some signals for consistency https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=18 <div><strong>Rev 18 - JonasDC</strong> (4 file(s) modified)</div><div>updated stages with comments and renamed some signals for consistency</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br /> JonasDC Wed, 24 Oct 2012 13:25:06 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=18 updated files with descriptive comments and removed unnecessary signals in ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=17 <div><strong>Rev 17 - JonasDC</strong> (3 file(s) modified)</div><div>updated files with descriptive comments and removed unnecessary signals in ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_cell_block.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br /> JonasDC Wed, 24 Oct 2012 08:25:16 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=17 package with modified generic parameter for register_n https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=16 <div><strong>Rev 16 - JonasDC</strong> (1 file(s) modified)</div><div>package with modified generic parameter for register_n</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br /> JonasDC Tue, 23 Oct 2012 19:20:35 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=16 changed generic for register width from n to width for ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=15 <div><strong>Rev 15 - JonasDC</strong> (4 file(s) modified)</div><div>changed generic for register width from n to width for ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/register_n.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br /> JonasDC Tue, 23 Oct 2012 19:15:55 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=15
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