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https://opencores.org/websvn//websvn/listing?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&
Fri, 29 Mar 2024 08:37:32 +0100FeedCreator 1.7.2big update, the mod_sim_exp core now has a selectable ram ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=69
<div><strong>Rev 69 - JonasDC</strong> (6 file(s) modified)</div><div>big update, the mod_sim_exp core now has a selectable ram ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />/mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />JonasDCWed, 06 Mar 2013 15:19:04 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=69added memory modules for modulus and operands for FPGA's that ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=67
<div><strong>Rev 67 - JonasDC</strong> (2 file(s) modified)</div><div>added memory modules for modulus and operands for FPGA's that ...</div>+ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />JonasDCWed, 06 Mar 2013 12:16:29 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=67updated plb interface, now modulus is selectable and, fifo depth ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=65
<div><strong>Rev 65 - JonasDC</strong> (4 file(s) modified)</div><div>updated plb interface, now modulus is selectable and, fifo depth ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />JonasDCTue, 26 Feb 2013 20:15:46 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=65now using a generic description of the ram for the ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=63
<div><strong>Rev 63 - JonasDC</strong> (5 file(s) modified)</div><div>now using a generic description of the ram for the ...</div>+ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem_gen.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />JonasDCTue, 26 Feb 2013 14:45:30 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=63generic version of the fifo, not device specific anymore, uses ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=60
<div><strong>Rev 60 - JonasDC</strong> (3 file(s) modified)</div><div>generic version of the fifo, not device specific anymore, uses ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_generic.vhd<br />JonasDCSat, 23 Feb 2013 21:45:26 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=60added templates that correctly infer RAM, for dual port en ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=59
<div><strong>Rev 59 - JonasDC</strong> (3 file(s) modified)</div><div>added templates that correctly infer RAM, for dual port en ...</div>+ /mod_sim_exp/trunk/rtl/vhdl/core/std_functions.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_generic.vhd<br />JonasDCSat, 23 Feb 2013 21:15:49 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=59updated resource usage in comments
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=55
<div><strong>Rev 55 - JonasDC</strong> (1 file(s) modified)</div><div>updated resource usage in comments</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />JonasDCTue, 19 Feb 2013 21:50:23 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=55generic fifo design: correctrly inferred by xilinx and altera
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=54
<div><strong>Rev 54 - JonasDC</strong> (1 file(s) modified)</div><div>generic fifo design: correctrly inferred by xilinx and altera</div>+ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />JonasDCTue, 19 Feb 2013 21:37:39 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=54chance run_auto port or mod_sim_exp_core to exp_m
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=45
<div><strong>Rev 45 - JonasDC</strong> (3 file(s) modified)</div><div>chance run_auto port or mod_sim_exp_core to exp_m</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />JonasDCSat, 01 Dec 2012 13:56:05 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=45made the core parameters generics
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=43
<div><strong>Rev 43 - JonasDC</strong> (6 file(s) modified)</div><div>made the core parameters generics</div>~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/multiplier_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mont_mult1536.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />JonasDCTue, 27 Nov 2012 20:27:53 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=43removed deprecated files from version control
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=41
<div><strong>Rev 41 - JonasDC</strong> (8 file(s) modified)</div><div>removed deprecated files from version control</div>- /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/systolic_pipeline.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />JonasDCWed, 21 Nov 2012 12:33:22 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=41changed files to remove warnings from synthesis
last cell logic is ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=39
<div><strong>Rev 39 - JonasDC</strong> (8 file(s) modified)</div><div>changed files to remove warnings from synthesis<br />
last cell logic is ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/autorun_cntrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_last_cell_logic.vhd<br />JonasDCMon, 12 Nov 2012 21:18:13 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=39deprecated design files because of new pipeline structure, will be ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=38
<div><strong>Rev 38 - JonasDC</strong> (6 file(s) modified)</div><div>deprecated design files because of new pipeline structure, will be ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/systolic_pipeline.vhd<br />JonasDCMon, 12 Nov 2012 15:44:05 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=38changed names of some generics of the multiplier.
moved the parameters ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=37
<div><strong>Rev 37 - JonasDC</strong> (6 file(s) modified)</div><div>changed names of some generics of the multiplier.<br />
moved the parameters ...</div>~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_multiplier.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />JonasDCThu, 08 Nov 2012 18:46:15 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=37found bug in new pipeline structure, now working properly. (tested ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=36
<div><strong>Rev 36 - JonasDC</strong> (2 file(s) modified)</div><div>found bug in new pipeline structure, now working properly. (tested ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />JonasDCWed, 07 Nov 2012 22:36:19 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=36operand memory now supports custom operand widths, the internal memory ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=34
<div><strong>Rev 34 - JonasDC</strong> (3 file(s) modified)</div><div>operand memory now supports custom operand widths, the internal memory ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />JonasDCWed, 07 Nov 2012 19:01:11 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=34default pipeline changed to old version, there seems to be ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=33
<div><strong>Rev 33 - JonasDC</strong> (1 file(s) modified)</div><div>default pipeline changed to old version, there seems to be ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />JonasDCWed, 07 Nov 2012 16:11:50 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=33new systolic pipeline structure now has split pipeline support, tested ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=32
<div><strong>Rev 32 - JonasDC</strong> (3 file(s) modified)</div><div>new systolic pipeline structure now has split pipeline support, tested ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_multiplier.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />JonasDCWed, 07 Nov 2012 15:12:34 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=32put first cell logic of the pipeline in a separate ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=31
<div><strong>Rev 31 - JonasDC</strong> (4 file(s) modified)</div><div>put first cell logic of the pipeline in a separate ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_first_cell_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />JonasDCWed, 07 Nov 2012 10:01:55 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=31put last cell logic of the pipeline in a separate ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=30
<div><strong>Rev 30 - JonasDC</strong> (4 file(s) modified)</div><div>put last cell logic of the pipeline in a separate ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_last_cell_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />JonasDCWed, 07 Nov 2012 09:37:37 +0100https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=30