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mod_sim_exp
WebSVN RSS feed - mod_sim_exp
https://opencores.org/websvn//websvn/listing?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2Fmod_sim_exp_core.vhd&
Fri, 29 Mar 2024 06:15:27 +0100
FeedCreator 1.7.2
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changes in makefile, and fifo's are now also in ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=97
<div><strong>Rev 97 - JonasDC</strong> (2 file(s) modified)</div><div>changes in makefile, and fifo's are now also in ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />
JonasDC
Wed, 17 Jul 2013 13:45:38 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=97
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BIG update: core now supports different clock speed for the ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=94
<div><strong>Rev 94 - JonasDC</strong> (38 file(s) modified)</div><div>BIG update: core now supports different clock speed for the ...</div>~ /mod_sim_exp/trunk/bench/vhdl/axi_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/msec_axi_tb.vhd<br />+ /mod_sim_exp/trunk/rtl/verilog<br />+ /mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc.v<br />+ /mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc_gray.v<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/clk_sync.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/pulse_cdc.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw5_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw5_syr.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw7_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw7_syr.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw5_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw5_syr.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw7_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw7_syr.html<br />~ /mod_sim_exp/trunk/syn/xilinx/src/operands_sp.xco<br />~ /mod_sim_exp/trunk/syn/xilinx/src/operand_dp.xco<br />
JonasDC
Wed, 03 Jul 2013 17:20:18 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=94
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reverted changes from previous revision, updated AXI version with testbench
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=90
<div><strong>Rev 90 - JonasDC</strong> (19 file(s) modified)</div><div>reverted changes from previous revision, updated AXI version with testbench</div>+ /mod_sim_exp/trunk/bench/vhdl/msec_axi_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />
JonasDC
Thu, 27 Jun 2013 18:31:38 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=90
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updated vhdl files so now different clock frequencies are posible ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=89
<div><strong>Rev 89 - JonasDC</strong> (17 file(s) modified)</div><div>updated vhdl files so now different clock frequencies are posible ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd<br />
JonasDC
Wed, 24 Apr 2013 20:19:10 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=89
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AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=84
<div><strong>Rev 84 - JonasDC</strong> (9 file(s) modified)</div><div>AXI-Lite interface updated, now tested and verified on Xilinx FPGA<br />
renamed ...</div>/mod_sim_exp/trunk/bench/vhdl/axi_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/interface/axi/axi_lite_slave.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />
JonasDC
Wed, 17 Apr 2013 10:09:11 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=84
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made rw_address a vector of a fixed width
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=75
<div><strong>Rev 75 - JonasDC</strong> (3 file(s) modified)</div><div>made rw_address a vector of a fixed width</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />
JonasDC
Mon, 11 Mar 2013 10:50:34 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=75
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removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=74
<div><strong>Rev 74 - JonasDC</strong> (2 file(s) modified)</div><div>removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />
JonasDC
Fri, 08 Mar 2013 14:44:16 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=74
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big update, the mod_sim_exp core now has a selectable ram ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=69
<div><strong>Rev 69 - JonasDC</strong> (6 file(s) modified)</div><div>big update, the mod_sim_exp core now has a selectable ram ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />/mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />
JonasDC
Wed, 06 Mar 2013 15:19:04 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=69
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now using a generic description of the ram for the ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=63
<div><strong>Rev 63 - JonasDC</strong> (5 file(s) modified)</div><div>now using a generic description of the ram for the ...</div>+ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem_gen.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />
JonasDC
Tue, 26 Feb 2013 14:45:30 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=63
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chance run_auto port or mod_sim_exp_core to exp_m
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=45
<div><strong>Rev 45 - JonasDC</strong> (3 file(s) modified)</div><div>chance run_auto port or mod_sim_exp_core to exp_m</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />
JonasDC
Sat, 01 Dec 2012 13:56:05 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=45
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made the core parameters generics
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=43
<div><strong>Rev 43 - JonasDC</strong> (6 file(s) modified)</div><div>made the core parameters generics</div>~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/multiplier_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mont_mult1536.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />
JonasDC
Tue, 27 Nov 2012 20:27:53 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=43
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changed files to remove warnings from synthesis
last cell logic is ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=39
<div><strong>Rev 39 - JonasDC</strong> (8 file(s) modified)</div><div>changed files to remove warnings from synthesis<br />
last cell logic is ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/autorun_cntrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_last_cell_logic.vhd<br />
JonasDC
Mon, 12 Nov 2012 21:18:13 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=39
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changed names of some generics of the multiplier.
moved the parameters ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=37
<div><strong>Rev 37 - JonasDC</strong> (6 file(s) modified)</div><div>changed names of some generics of the multiplier.<br />
moved the parameters ...</div>~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_multiplier.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />
JonasDC
Thu, 08 Nov 2012 18:46:15 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=37
-
found bug in new pipeline structure, now working properly. (tested ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=36
<div><strong>Rev 36 - JonasDC</strong> (2 file(s) modified)</div><div>found bug in new pipeline structure, now working properly. (tested ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />
JonasDC
Wed, 07 Nov 2012 22:36:19 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=36
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operand memory now supports custom operand widths, the internal memory ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=34
<div><strong>Rev 34 - JonasDC</strong> (3 file(s) modified)</div><div>operand memory now supports custom operand widths, the internal memory ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />
JonasDC
Wed, 07 Nov 2012 19:01:11 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=34
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default pipeline changed to old version, there seems to be ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=33
<div><strong>Rev 33 - JonasDC</strong> (1 file(s) modified)</div><div>default pipeline changed to old version, there seems to be ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />
JonasDC
Wed, 07 Nov 2012 16:11:50 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=33
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new systolic pipeline structure now has split pipeline support, tested ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=32
<div><strong>Rev 32 - JonasDC</strong> (3 file(s) modified)</div><div>new systolic pipeline structure now has split pipeline support, tested ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_multiplier.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />
JonasDC
Wed, 07 Nov 2012 15:12:34 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=32
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changed names of top-level module to mod_sim_exp_core
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=24
<div><strong>Rev 24 - JonasDC</strong> (8 file(s) modified)</div><div>changed names of top-level module to mod_sim_exp_core</div>~ /mod_sim_exp/trunk<br />+ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />- /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />
JonasDC
Sat, 03 Nov 2012 10:43:00 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=24
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updated vhdl sources with new header according to OC design ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=3
<div><strong>Rev 3 - JonasDC</strong> (36 file(s) modified)</div><div>updated vhdl sources with new header according to OC design ...</div>~ /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_block.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/autorun_cntrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_adder.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_mux.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/d_flip_flop.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operands_sp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/register_1b.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/register_n.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_cell_block.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/std_logic_textio.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/stepping_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/systolic_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/x_shift_reg.vhd<br />+ /mod_sim_exp/trunk/sim<br />+ /mod_sim_exp/trunk/sim/Makefile<br />+ /mod_sim_exp/trunk/sim/mod_sim_exp.do<br />+ /mod_sim_exp/trunk/sim/out<br />+ /mod_sim_exp/trunk/sim/out/sim_output.txt<br />+ /mod_sim_exp/trunk/sim/src<br />+ /mod_sim_exp/trunk/sim/src/sim_input.txt<br />
JonasDC
Mon, 22 Oct 2012 19:08:31 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=3
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First version of VHDL source(working), still contains xilinx primitives and ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=2
<div><strong>Rev 2 - JonasDC</strong> (37 file(s) modified)</div><div>First version of VHDL source(working), still contains xilinx primitives and ...</div>+ /mod_sim_exp/trunk/bench<br />+ /mod_sim_exp/trunk/bench/vhdl<br />+ /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd<br />+ /mod_sim_exp/trunk/rtl<br />+ /mod_sim_exp/trunk/rtl/vhdl<br />+ /mod_sim_exp/trunk/rtl/vhdl/core<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/adder_block.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/autorun_cntrl.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_adder.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_mux.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/d_flip_flop.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operands_sp.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/register_1b.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/register_n.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/standard_cell_block.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/std_logic_textio.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/stepping_logic.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/systolic_pipeline.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/x_shift_reg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/plb<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mont_mult1536.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />
JonasDC
Thu, 18 Oct 2012 13:14:22 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fcore%2F&rev=2
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