URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Error creating feed file, please check write permissions.
mod_sim_exp
WebSVN RSS feed - mod_sim_exp
https://opencores.org/websvn//websvn/listing?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Faxi%2Fmsec_ipcore_axilite.vhd&
Mon, 18 May 2026 02:43:57 +0100
FeedCreator 1.7.2
-
BIG update: core now supports different clock speed for the ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Faxi%2F&rev=94
<div><strong>Rev 94 - JonasDC</strong> (38 file(s) modified)</div><div>BIG update: core now supports different clock speed for the ...</div>~ /mod_sim_exp/trunk/bench/vhdl/axi_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/msec_axi_tb.vhd<br />+ /mod_sim_exp/trunk/rtl/verilog<br />+ /mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc.v<br />+ /mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc_gray.v<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/clk_sync.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/pulse_cdc.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw5_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw5_syr.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw7_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw7_syr.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw5_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw5_syr.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw7_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw7_syr.html<br />~ /mod_sim_exp/trunk/syn/xilinx/src/operands_sp.xco<br />~ /mod_sim_exp/trunk/syn/xilinx/src/operand_dp.xco<br />
JonasDC
Wed, 03 Jul 2013 17:20:18 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Faxi%2F&rev=94
-
changed interrupt structure of AXI4-Lite interface. Now the interrupt has ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Faxi%2F&rev=91
<div><strong>Rev 91 - JonasDC</strong> (1 file(s) modified)</div><div>changed interrupt structure of AXI4-Lite interface. Now the interrupt has ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />
JonasDC
Sat, 29 Jun 2013 09:07:21 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Faxi%2F&rev=91
-
reverted changes from previous revision, updated AXI version with testbench
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Faxi%2F&rev=90
<div><strong>Rev 90 - JonasDC</strong> (19 file(s) modified)</div><div>reverted changes from previous revision, updated AXI version with testbench</div>+ /mod_sim_exp/trunk/bench/vhdl/msec_axi_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />
JonasDC
Thu, 27 Jun 2013 18:31:38 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Faxi%2F&rev=90
-
updated vhdl files so now different clock frequencies are posible ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Faxi%2F&rev=89
<div><strong>Rev 89 - JonasDC</strong> (17 file(s) modified)</div><div>updated vhdl files so now different clock frequencies are posible ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd<br />
JonasDC
Wed, 24 Apr 2013 20:19:10 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Faxi%2F&rev=89
-
update on previous
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Faxi%2F&rev=86
<div><strong>Rev 86 - JonasDC</strong> (1 file(s) modified)</div><div>update on previous</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />
JonasDC
Thu, 18 Apr 2013 18:45:24 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Faxi%2F&rev=86
-
changed so that reset now also affects slave register
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Faxi%2F&rev=85
<div><strong>Rev 85 - JonasDC</strong> (1 file(s) modified)</div><div>changed so that reset now also affects slave register</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />
JonasDC
Thu, 18 Apr 2013 18:42:46 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Faxi%2F&rev=85
-
AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Faxi%2F&rev=84
<div><strong>Rev 84 - JonasDC</strong> (9 file(s) modified)</div><div>AXI-Lite interface updated, now tested and verified on Xilinx FPGA<br />
renamed ...</div>/mod_sim_exp/trunk/bench/vhdl/axi_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/interface/axi/axi_lite_slave.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />
JonasDC
Wed, 17 Apr 2013 10:09:11 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Faxi%2F&rev=84
-
added first version of axi-lite interface and testbench for basic ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Faxi%2F&rev=82
<div><strong>Rev 82 - JonasDC</strong> (3 file(s) modified)</div><div>added first version of axi-lite interface and testbench for basic ...</div>+ /mod_sim_exp/trunk/bench/vhdl/axi_tb.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/axi<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/axi_lite_slave.vhd<br />
JonasDC
Fri, 29 Mar 2013 13:17:23 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Faxi%2F&rev=82
© copyright 1999-2026
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.