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mod_sim_exp
WebSVN RSS feed - mod_sim_exp
https://opencores.org/websvn//websvn/listing?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&
Thu, 28 Mar 2024 14:00:03 +0100
FeedCreator 1.7.2
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BIG update: core now supports different clock speed for the ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=94
<div><strong>Rev 94 - JonasDC</strong> (38 file(s) modified)</div><div>BIG update: core now supports different clock speed for the ...</div>~ /mod_sim_exp/trunk/bench/vhdl/axi_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/msec_axi_tb.vhd<br />+ /mod_sim_exp/trunk/rtl/verilog<br />+ /mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc.v<br />+ /mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc_gray.v<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/clk_sync.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/pulse_cdc.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw5_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw5_syr.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw7_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw7_syr.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw5_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw5_syr.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw7_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw7_syr.html<br />~ /mod_sim_exp/trunk/syn/xilinx/src/operands_sp.xco<br />~ /mod_sim_exp/trunk/syn/xilinx/src/operand_dp.xco<br />
JonasDC
Wed, 03 Jul 2013 17:20:18 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=94
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AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=84
<div><strong>Rev 84 - JonasDC</strong> (9 file(s) modified)</div><div>AXI-Lite interface updated, now tested and verified on Xilinx FPGA<br />
renamed ...</div>/mod_sim_exp/trunk/bench/vhdl/axi_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/interface/axi/axi_lite_slave.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />
JonasDC
Wed, 17 Apr 2013 10:09:11 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=84
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found fault in code, now synthesizes normally
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=77
<div><strong>Rev 77 - JonasDC</strong> (1 file(s) modified)</div><div>found fault in code, now synthesizes normally</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />
JonasDC
Wed, 13 Mar 2013 21:48:20 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=77
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removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=74
<div><strong>Rev 74 - JonasDC</strong> (2 file(s) modified)</div><div>removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />
JonasDC
Fri, 08 Mar 2013 14:44:16 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=74
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updated plb interface, mem_style and device generics added
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=73
<div><strong>Rev 73 - JonasDC</strong> (3 file(s) modified)</div><div>updated plb interface, mem_style and device generics added</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mont_mult1536.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />
JonasDC
Thu, 07 Mar 2013 15:32:03 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=73
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updated plb interface, now modulus is selectable and, fifo depth ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=65
<div><strong>Rev 65 - JonasDC</strong> (4 file(s) modified)</div><div>updated plb interface, now modulus is selectable and, fifo depth ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />
JonasDC
Tue, 26 Feb 2013 20:15:46 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=65
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chance run_auto port or mod_sim_exp_core to exp_m
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=45
<div><strong>Rev 45 - JonasDC</strong> (3 file(s) modified)</div><div>chance run_auto port or mod_sim_exp_core to exp_m</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />
JonasDC
Sat, 01 Dec 2012 13:56:05 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=45
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toplevel of the Modular Simultaneous Exponentiation IP core for the ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=44
<div><strong>Rev 44 - JonasDC</strong> (1 file(s) modified)</div><div>toplevel of the Modular Simultaneous Exponentiation IP core for the ...</div>+ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />
JonasDC
Tue, 27 Nov 2012 20:29:09 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=44
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made the core parameters generics
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=43
<div><strong>Rev 43 - JonasDC</strong> (6 file(s) modified)</div><div>made the core parameters generics</div>~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/multiplier_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mont_mult1536.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />
JonasDC
Tue, 27 Nov 2012 20:27:53 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=43
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corrected wrong library name for mod_sim_exp_pkg
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=42
<div><strong>Rev 42 - JonasDC</strong> (1 file(s) modified)</div><div>corrected wrong library name for mod_sim_exp_pkg</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />
JonasDC
Wed, 21 Nov 2012 12:37:15 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=42
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adjusted core instantiation to new core module name
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=40
<div><strong>Rev 40 - JonasDC</strong> (1 file(s) modified)</div><div>adjusted core instantiation to new core module name</div>~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />
JonasDC
Tue, 13 Nov 2012 08:31:43 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=40
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First version of VHDL source(working), still contains xilinx primitives and ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=2
<div><strong>Rev 2 - JonasDC</strong> (37 file(s) modified)</div><div>First version of VHDL source(working), still contains xilinx primitives and ...</div>+ /mod_sim_exp/trunk/bench<br />+ /mod_sim_exp/trunk/bench/vhdl<br />+ /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd<br />+ /mod_sim_exp/trunk/rtl<br />+ /mod_sim_exp/trunk/rtl/vhdl<br />+ /mod_sim_exp/trunk/rtl/vhdl/core<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/adder_block.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/autorun_cntrl.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_adder.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_mux.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/d_flip_flop.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operands_sp.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/register_1b.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/register_n.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/standard_cell_block.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/std_logic_textio.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/stepping_logic.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/systolic_pipeline.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/x_shift_reg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/plb<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mont_mult1536.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />
JonasDC
Thu, 18 Oct 2012 13:14:22 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Finterface%2Fplb%2F&rev=2
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