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mod_sim_exp
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https://opencores.org/websvn//websvn/listing?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&
Thu, 28 Mar 2024 14:14:44 +0100
FeedCreator 1.7.2
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reverted changes from previous revision, updated AXI version with testbench
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=90
<div><strong>Rev 90 - JonasDC</strong> (19 file(s) modified)</div><div>reverted changes from previous revision, updated AXI version with testbench</div>+ /mod_sim_exp/trunk/bench/vhdl/msec_axi_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />
JonasDC
Thu, 27 Jun 2013 18:31:38 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=90
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updated vhdl files so now different clock frequencies are posible ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=89
<div><strong>Rev 89 - JonasDC</strong> (17 file(s) modified)</div><div>updated vhdl files so now different clock frequencies are posible ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd<br />
JonasDC
Wed, 24 Apr 2013 20:19:10 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=89
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now using values from mod_sim_exp_pkg instead of direct entity
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=83
<div><strong>Rev 83 - JonasDC</strong> (3 file(s) modified)</div><div>now using values from mod_sim_exp_pkg instead of direct entity</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />
JonasDC
Mon, 15 Apr 2013 09:18:25 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=83
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added asymmetric ram structures to support a more performant ramstyle.
defined ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=66
<div><strong>Rev 66 - JonasDC</strong> (4 file(s) modified)</div><div>added asymmetric ram structures to support a more performant ramstyle.<br />
defined ...</div>+ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd<br />
JonasDC
Wed, 06 Mar 2013 12:05:05 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=66
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not used anymore
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=62
<div><strong>Rev 62 - JonasDC</strong> (3 file(s) modified)</div><div>not used anymore</div>- /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_altera.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_xilinx.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_xilinx.vhd<br />
JonasDC
Tue, 26 Feb 2013 12:01:21 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=62
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updated comments, added optional altera constraint
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=61
<div><strong>Rev 61 - JonasDC</strong> (2 file(s) modified)</div><div>updated comments, added optional altera constraint</div>~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_generic.vhd<br />
JonasDC
Tue, 26 Feb 2013 12:00:44 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=61
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generic version of the fifo, not device specific anymore, uses ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=60
<div><strong>Rev 60 - JonasDC</strong> (3 file(s) modified)</div><div>generic version of the fifo, not device specific anymore, uses ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_generic.vhd<br />
JonasDC
Sat, 23 Feb 2013 21:45:26 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=60
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added templates that correctly infer RAM, for dual port en ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=59
<div><strong>Rev 59 - JonasDC</strong> (3 file(s) modified)</div><div>added templates that correctly infer RAM, for dual port en ...</div>+ /mod_sim_exp/trunk/rtl/vhdl/core/std_functions.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_generic.vhd<br />
JonasDC
Sat, 23 Feb 2013 21:15:49 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=59
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correctly inferred ram for altera dual port ram
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=53
<div><strong>Rev 53 - JonasDC</strong> (1 file(s) modified)</div><div>correctly inferred ram for altera dual port ram</div>+ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_altera.vhd<br />
JonasDC
Tue, 19 Feb 2013 14:59:11 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=53
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correct inferring of blockram, no additional resources.
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=52
<div><strong>Rev 52 - JonasDC</strong> (1 file(s) modified)</div><div>correct inferring of blockram, no additional resources.</div>~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_xilinx.vhd<br />
JonasDC
Tue, 19 Feb 2013 14:34:52 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=52
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true dual port ram for xilinx
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=51
<div><strong>Rev 51 - JonasDC</strong> (1 file(s) modified)</div><div>true dual port ram for xilinx</div>+ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_xilinx.vhd<br />
JonasDC
Tue, 19 Feb 2013 13:53:22 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=51
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added folder for ram descriptions
added experimental simple dual port ram ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=50
<div><strong>Rev 50 - JonasDC</strong> (2 file(s) modified)</div><div>added folder for ram descriptions<br />
added experimental simple dual port ram ...</div>+ /mod_sim_exp/trunk/rtl/vhdl/ram<br />+ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_xilinx.vhd<br />
JonasDC
Tue, 19 Feb 2013 13:51:30 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Frtl%2Fvhdl%2Fram%2F&rev=50
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