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mod_sim_exp WebSVN RSS feed - mod_sim_exp https://opencores.org/websvn//websvn/listing?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F& Mon, 03 Oct 2022 17:02:54 +0100 FeedCreator 1.7.2 AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=84 <div><strong>Rev 84 - JonasDC</strong> (9 file(s) modified)</div><div>AXI-Lite interface updated, now tested and verified on Xilinx FPGA<br /> renamed ...</div>/mod_sim_exp/trunk/bench/vhdl/axi_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/interface/axi/axi_lite_slave.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br /> JonasDC Wed, 17 Apr 2013 10:09:11 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=84 updated testbench for use with new core parameters updated makefile, added ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=70 <div><strong>Rev 70 - JonasDC</strong> (5 file(s) modified)</div><div>updated testbench for use with new core parameters<br /> updated makefile, added ...</div>~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/sim<br />~ /mod_sim_exp/trunk/sim/Makefile<br />~ /mod_sim_exp/trunk/sim/mod_sim_exp.do<br />~ /mod_sim_exp/trunk/sim/out<br /> JonasDC Wed, 06 Mar 2013 15:21:18 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=70 updated plb interface, now modulus is selectable and, fifo depth ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=65 <div><strong>Rev 65 - JonasDC</strong> (4 file(s) modified)</div><div>updated plb interface, now modulus is selectable and, fifo depth ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br /> JonasDC Tue, 26 Feb 2013 20:15:46 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=65 removed deprecated files from version control https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=41 <div><strong>Rev 41 - JonasDC</strong> (8 file(s) modified)</div><div>removed deprecated files from version control</div>- /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/systolic_pipeline.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br /> JonasDC Wed, 21 Nov 2012 12:33:22 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=41 new test values, 1st exponentiation gives error on result with ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=35 <div><strong>Rev 35 - JonasDC</strong> (1 file(s) modified)</div><div>new test values, 1st exponentiation gives error on result with ...</div>~ /mod_sim_exp/trunk/sim/src/sim_input.txt<br /> JonasDC Wed, 07 Nov 2012 20:08:23 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=35 put first cell logic of the pipeline in a separate ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=31 <div><strong>Rev 31 - JonasDC</strong> (4 file(s) modified)</div><div>put first cell logic of the pipeline in a separate ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_first_cell_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br /> JonasDC Wed, 07 Nov 2012 10:01:55 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=31 put last cell logic of the pipeline in a separate ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=30 <div><strong>Rev 30 - JonasDC</strong> (4 file(s) modified)</div><div>put last cell logic of the pipeline in a separate ...</div>~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/sys_last_cell_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br /> JonasDC Wed, 07 Nov 2012 09:37:37 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=30 updated makefile for new pipeline sources https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=28 <div><strong>Rev 28 - JonasDC</strong> (1 file(s) modified)</div><div>updated makefile for new pipeline sources</div>~ /mod_sim_exp/trunk/sim/Makefile<br /> JonasDC Tue, 06 Nov 2012 19:43:40 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=28 test input values for multiplier_tb https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=27 <div><strong>Rev 27 - JonasDC</strong> (1 file(s) modified)</div><div>test input values for multiplier_tb</div>+ /mod_sim_exp/trunk/sim/src/sim_mult_input.txt<br /> JonasDC Tue, 06 Nov 2012 19:43:05 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=27 changed names of top-level module to mod_sim_exp_core https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=24 <div><strong>Rev 24 - JonasDC</strong> (8 file(s) modified)</div><div>changed names of top-level module to mod_sim_exp_core</div>~ /mod_sim_exp/trunk<br />+ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />- /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br /> JonasDC Sat, 03 Nov 2012 10:43:00 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=24 simulation output folder https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=11 <div><strong>Rev 11 - JonasDC</strong> (1 file(s) modified)</div><div>simulation output folder</div>~ /mod_sim_exp/trunk/sim/out<br /> JonasDC Tue, 23 Oct 2012 16:22:17 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=11 not needed on svn, is generated by testbench https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=5 <div><strong>Rev 5 - JonasDC</strong> (1 file(s) modified)</div><div>not needed on svn, is generated by testbench</div>- /mod_sim_exp/trunk/sim/out/sim_output.txt<br /> JonasDC Tue, 23 Oct 2012 10:39:08 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=5 updated vhdl sources with new header according to OC design ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=3 <div><strong>Rev 3 - JonasDC</strong> (36 file(s) modified)</div><div>updated vhdl sources with new header according to OC design ...</div>~ /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_block.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/autorun_cntrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_adder.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_mux.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/d_flip_flop.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operands_sp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/register_1b.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/register_n.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_cell_block.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/std_logic_textio.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/stepping_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/systolic_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/x_shift_reg.vhd<br />+ /mod_sim_exp/trunk/sim<br />+ /mod_sim_exp/trunk/sim/Makefile<br />+ /mod_sim_exp/trunk/sim/mod_sim_exp.do<br />+ /mod_sim_exp/trunk/sim/out<br />+ /mod_sim_exp/trunk/sim/out/sim_output.txt<br />+ /mod_sim_exp/trunk/sim/src<br />+ /mod_sim_exp/trunk/sim/src/sim_input.txt<br /> JonasDC Mon, 22 Oct 2012 19:08:31 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2F&rev=3
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