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mod_sim_exp WebSVN RSS feed - mod_sim_exp https://opencores.org/websvn//websvn/listing?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2Fsrc%2F& Thu, 28 Mar 2024 18:18:18 +0100 FeedCreator 1.7.2 new test values, 1st exponentiation gives error on result with ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2Fsrc%2F&rev=35 <div><strong>Rev 35 - JonasDC</strong> (1 file(s) modified)</div><div>new test values, 1st exponentiation gives error on result with ...</div>~ /mod_sim_exp/trunk/sim/src/sim_input.txt<br /> JonasDC Wed, 07 Nov 2012 20:08:23 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2Fsrc%2F&rev=35 test input values for multiplier_tb https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2Fsrc%2F&rev=27 <div><strong>Rev 27 - JonasDC</strong> (1 file(s) modified)</div><div>test input values for multiplier_tb</div>+ /mod_sim_exp/trunk/sim/src/sim_mult_input.txt<br /> JonasDC Tue, 06 Nov 2012 19:43:05 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2Fsrc%2F&rev=27 updated vhdl sources with new header according to OC design ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2Fsrc%2F&rev=3 <div><strong>Rev 3 - JonasDC</strong> (36 file(s) modified)</div><div>updated vhdl sources with new header according to OC design ...</div>~ /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_block.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/adder_n.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/autorun_cntrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_adder.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/cell_1b_mux.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/counter_sync.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/d_flip_flop.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/first_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/last_stage.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_ctrl.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mont_mult_sys_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/multiplier_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operands_sp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/register_1b.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/register_n.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_cell_block.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/standard_stage.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/std_logic_textio.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/stepping_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/systolic_pipeline.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/x_shift_reg.vhd<br />+ /mod_sim_exp/trunk/sim<br />+ /mod_sim_exp/trunk/sim/Makefile<br />+ /mod_sim_exp/trunk/sim/mod_sim_exp.do<br />+ /mod_sim_exp/trunk/sim/out<br />+ /mod_sim_exp/trunk/sim/out/sim_output.txt<br />+ /mod_sim_exp/trunk/sim/src<br />+ /mod_sim_exp/trunk/sim/src/sim_input.txt<br /> JonasDC Mon, 22 Oct 2012 19:08:31 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsim%2Fsrc%2F&rev=3
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