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mod_sim_exp WebSVN RSS feed - mod_sim_exp https://opencores.org/websvn//websvn/listing?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsyn%2Fxilinx%2F& Thu, 28 Mar 2024 13:54:03 +0100 FeedCreator 1.7.2 BIG update: core now supports different clock speed for the ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsyn%2Fxilinx%2F&rev=94 <div><strong>Rev 94 - JonasDC</strong> (38 file(s) modified)</div><div>BIG update: core now supports different clock speed for the ...</div>~ /mod_sim_exp/trunk/bench/vhdl/axi_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/msec_axi_tb.vhd<br />+ /mod_sim_exp/trunk/rtl/verilog<br />+ /mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc.v<br />+ /mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc_gray.v<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/clk_sync.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/pulse_cdc.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw5_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw5_syr.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw7_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw7_syr.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw5_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw5_syr.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw7_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw7_syr.html<br />~ /mod_sim_exp/trunk/syn/xilinx/src/operands_sp.xco<br />~ /mod_sim_exp/trunk/syn/xilinx/src/operand_dp.xco<br /> JonasDC Wed, 03 Jul 2013 17:20:18 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsyn%2Fxilinx%2F&rev=94 deleted old resources https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsyn%2Fxilinx%2F&rev=72 <div><strong>Rev 72 - JonasDC</strong> (8 file(s) modified)</div><div>deleted old resources</div>- /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm<br />- /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_res.htm_files<br />- /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm<br />- /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files<br />- /mod_sim_exp/trunk/syn/xilinx/ver010_msec_sum.html<br />- /mod_sim_exp/trunk/syn/xilinx/ver010_msec_syn.html<br />- /mod_sim_exp/trunk/syn/xilinx/ver011_msec_genRAM_sum.html<br />- /mod_sim_exp/trunk/syn/xilinx/ver011_msec_genRAM_syn.html<br /> JonasDC Wed, 06 Mar 2013 15:29:03 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsyn%2Fxilinx%2F&rev=72 added synthesis report for altera and xilinx for the new ... https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsyn%2Fxilinx%2F&rev=71 <div><strong>Rev 71 - JonasDC</strong> (34 file(s) modified)</div><div>added synthesis report for altera and xilinx for the new ...</div>+ /mod_sim_exp/trunk/syn/altera/log<br />+ /mod_sim_exp/trunk/syn/altera/log/fifo<br />+ /mod_sim_exp/trunk/syn/altera/log/fifo/generic_mes.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/fifo/generic_sum.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/mod_sim_exp_core<br />+ /mod_sim_exp/trunk/syn/altera/log/mod_sim_exp_core/ver011_msec_genRAM_res.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/mod_sim_exp_core/ver011_msec_genRAM_sum.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/operand_mem<br />+ /mod_sim_exp/trunk/syn/altera/log/operand_mem/asym_mes.htm<br />+ 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/mod_sim_exp/trunk/syn/xilinx/log/operand_mem<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/asym_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/asym_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/generic_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/generic_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/xil_prim_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/xil_prim_syn.html<br />- /mod_sim_exp/trunk/syn/xilinx/operands_sp.pdf<br />+ /mod_sim_exp/trunk/syn/xilinx/src<br />+ /mod_sim_exp/trunk/syn/xilinx/src/operands_sp.xco<br />+ /mod_sim_exp/trunk/syn/xilinx/src/operand_dp.xco<br /> JonasDC Wed, 06 Mar 2013 15:27:23 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsyn%2Fxilinx%2F&rev=71 added synthesis reports of xilinx and altera https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsyn%2Fxilinx%2F&rev=64 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/mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/img/ui-icons_ffffff_256x240.png<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/js<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/js/jquery-ui.min.js<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/js/jquery.layout-latest.js<br />+ /mod_sim_exp/trunk/syn/altera/ver011_msec_genRAM_sum.htm_files/js/jquery.min.js<br />+ /mod_sim_exp/trunk/syn/xilinx<br />+ /mod_sim_exp/trunk/syn/xilinx/operands_sp.pdf<br />+ /mod_sim_exp/trunk/syn/xilinx/ver010_msec_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/ver010_msec_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/ver011_msec_genRAM_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/ver011_msec_genRAM_syn.html<br /> JonasDC Tue, 26 Feb 2013 14:49:12 +0100 https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsyn%2Fxilinx%2F&rev=64
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