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https://opencores.org/websvn//websvn/listing?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsyn%2Fxilinx%2Flog%2Ffifo%2F&
Fri, 29 Mar 2024 06:22:01 +0100
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BIG update: core now supports different clock speed for the ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsyn%2Fxilinx%2Flog%2Ffifo%2F&rev=94
<div><strong>Rev 94 - JonasDC</strong> (38 file(s) modified)</div><div>BIG update: core now supports different clock speed for the ...</div>~ /mod_sim_exp/trunk/bench/vhdl/axi_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd<br />~ /mod_sim_exp/trunk/bench/vhdl/msec_axi_tb.vhd<br />+ /mod_sim_exp/trunk/rtl/verilog<br />+ /mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc.v<br />+ /mod_sim_exp/trunk/rtl/verilog/generic_fifo_dc_gray.v<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/clk_sync.vhd<br />- /mod_sim_exp/trunk/rtl/vhdl/core/fifo_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/fifo_primitive.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/modulus_ram_gen.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_core.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_dp.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_mem.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/core/operand_ram_gen.vhd<br />+ /mod_sim_exp/trunk/rtl/vhdl/core/pulse_cdc.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/axi/msec_ipcore_axilite.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/mod_sim_exp_IPcore.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/interface/plb/user_logic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/dpram_generic.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpramblock_asym.vhd<br />~ /mod_sim_exp/trunk/rtl/vhdl/ram/tdpram_asym.vhd<br />~ /mod_sim_exp/trunk/sim/Makefile<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw5_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw5_syr.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw7_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_aw7_syr.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw5_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw5_syr.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw7_summary.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_dc_gray_aw7_syr.html<br />~ /mod_sim_exp/trunk/syn/xilinx/src/operands_sp.xco<br />~ /mod_sim_exp/trunk/syn/xilinx/src/operand_dp.xco<br />
JonasDC
Wed, 03 Jul 2013 17:20:18 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsyn%2Fxilinx%2Flog%2Ffifo%2F&rev=94
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added synthesis report for altera and xilinx for the new ...
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsyn%2Fxilinx%2Flog%2Ffifo%2F&rev=71
<div><strong>Rev 71 - JonasDC</strong> (34 file(s) modified)</div><div>added synthesis report for altera and xilinx for the new ...</div>+ /mod_sim_exp/trunk/syn/altera/log<br />+ /mod_sim_exp/trunk/syn/altera/log/fifo<br />+ /mod_sim_exp/trunk/syn/altera/log/fifo/generic_mes.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/fifo/generic_sum.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/mod_sim_exp_core<br />+ /mod_sim_exp/trunk/syn/altera/log/mod_sim_exp_core/ver011_msec_genRAM_res.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/mod_sim_exp_core/ver011_msec_genRAM_sum.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/operand_mem<br />+ /mod_sim_exp/trunk/syn/altera/log/operand_mem/asym_mes.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/operand_mem/asym_sum.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/operand_mem/generic_mes.htm<br />+ /mod_sim_exp/trunk/syn/altera/log/operand_mem/generic_sum.htm<br />+ /mod_sim_exp/trunk/syn/xilinx/log<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/generic_fifo_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/xil_prim_fifo_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/fifo/xil_prim_fifo_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/mod_sim_exp_core<br />+ /mod_sim_exp/trunk/syn/xilinx/log/mod_sim_exp_core/ver010_msec_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/mod_sim_exp_core/ver010_msec_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/mod_sim_exp_core/ver011_msec_genRAM_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/mod_sim_exp_core/ver011_msec_genRAM_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/asym_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/asym_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/generic_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/generic_syn.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/xil_prim_sum.html<br />+ /mod_sim_exp/trunk/syn/xilinx/log/operand_mem/xil_prim_syn.html<br />- /mod_sim_exp/trunk/syn/xilinx/operands_sp.pdf<br />+ /mod_sim_exp/trunk/syn/xilinx/src<br />+ /mod_sim_exp/trunk/syn/xilinx/src/operands_sp.xco<br />+ /mod_sim_exp/trunk/syn/xilinx/src/operand_dp.xco<br />
JonasDC
Wed, 06 Mar 2013 15:27:23 +0100
https://opencores.org/websvn//websvn/revision?repname=mod_sim_exp&path=%2Fmod_sim_exp%2Ftrunk%2Fsyn%2Fxilinx%2Flog%2Ffifo%2F&rev=71
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