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open8_urisc WebSVN RSS feed - open8_urisc https://opencores.org/websvn//websvn/listing?repname=open8_urisc&path=%2Fopen8_urisc%2F& Sat, 06 Jun 2026 01:46:34 +0100 FeedCreator 1.7.2 Added Notepad++ language definition file for the Open8_II ISA https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=291 <div><strong>Rev 291 - jshamlet</strong> (1 file(s) modified)</div><div>Added Notepad++ language definition file for the Open8_II ISA</div>+ /open8_urisc/trunk/Open8 Tools/Open8_II.xml<br /> jshamlet Tue, 04 May 2021 03:08:24 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=291 Added an additional generic &quot;Rotation_Ignores_Carry&quot; that removes the carry ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=290 <div><strong>Rev 290 - jshamlet</strong> (12 file(s) modified)</div><div>Added an additional generic &quot;Rotation_Ignores_Carry&quot; that removes the carry logic ...</div>~ /open8_urisc/trunk/Open8 Tools/open8_src/open8_as/main.c<br />~ /open8_urisc/trunk/Open8 Tools/open8_src/open8_as/makefile<br />~ /open8_urisc/trunk/Open8 Tools/open8_src/open8_as/opcodes_v8urisc.c<br />~ /open8_urisc/trunk/Open8 Tools/open8_src/open8_as/opcodes_v8urisc_tables.c<br />+ /open8_urisc/trunk/Open8 Tools/open8_src/open8_as/opcode_table_generator/gen.exe<br />~ /open8_urisc/trunk/Open8 Tools/open8_src/open8_as/opcode_table_generator/makefile<br />+ /open8_urisc/trunk/Open8 Tools/open8_src/open8_as/open8_as.exe<br />~ /open8_urisc/trunk/Open8 Tools/open8_src/open8_link/main.c<br />~ /open8_urisc/trunk/Open8 Tools/open8_src/open8_link/makefile<br />+ /open8_urisc/trunk/Open8 Tools/open8_src/open8_link/open8_link.exe<br />~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_cfg.vhd<br /> jshamlet Tue, 04 May 2021 03:06:31 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=290 Added back the delay for the cursor home command, since ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=289 <div><strong>Rev 289 - jshamlet</strong> (1 file(s) modified)</div><div>Added back the delay for the cursor home command, since ...</div>~ /open8_urisc/trunk/VHDL/o8_hd44780_if.vhd<br /> jshamlet Fri, 16 Apr 2021 16:24:27 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=289 Removed hard-wired R/Wn output and replaced it with a note ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=288 <div><strong>Rev 288 - jshamlet</strong> (1 file(s) modified)</div><div>Removed hard-wired R/Wn output and replaced it with a note ...</div>~ /open8_urisc/trunk/VHDL/o8_hd44780_if.vhd<br /> jshamlet Thu, 15 Apr 2021 20:11:34 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=288 Fixed mangled comments and revisioning dates. https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=287 <div><strong>Rev 287 - jshamlet</strong> (3 file(s) modified)</div><div>Fixed mangled comments and revisioning dates.</div>~ /open8_urisc/trunk/VHDL/hd44780_4b.vhd<br />~ /open8_urisc/trunk/VHDL/hd44780_8b.vhd<br />~ /open8_urisc/trunk/VHDL/o8_hd44780_if.vhd<br /> jshamlet Wed, 14 Apr 2021 20:57:39 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=287 Added initial cut of a &quot;universal&quot; character LCD driver. Allows ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=286 <div><strong>Rev 286 - jshamlet</strong> (3 file(s) modified)</div><div>Added initial cut of a &quot;universal&quot; character LCD driver. Allows ...</div>+ /open8_urisc/trunk/VHDL/hd44780_4b.vhd<br />+ /open8_urisc/trunk/VHDL/hd44780_8b.vhd<br />+ /open8_urisc/trunk/VHDL/o8_hd44780_if.vhd<br /> jshamlet Wed, 14 Apr 2021 20:37:56 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=286 Added checksum byte to vector tx/rx to avoid issues with ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=285 <div><strong>Rev 285 - jshamlet</strong> (2 file(s) modified)</div><div>Added checksum byte to vector tx/rx to avoid issues with ...</div>~ /open8_urisc/trunk/VHDL/o8_vector_rx.vhd<br />~ /open8_urisc/trunk/VHDL/vector_tx.vhd<br /> jshamlet Wed, 07 Apr 2021 17:36:56 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=285 Corrected the vhdl unit name and description for o8_7seg.vhd https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=284 <div><strong>Rev 284 - jshamlet</strong> (1 file(s) modified)</div><div>Corrected the vhdl unit name and description for o8_7seg.vhd</div>~ /open8_urisc/trunk/VHDL/o8_7seg.vhd<br /> jshamlet Tue, 15 Dec 2020 06:23:04 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=284 Altered SDLC bitclock check on TX to NOT block when ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=283 <div><strong>Rev 283 - jshamlet</strong> (1 file(s) modified)</div><div>Altered SDLC bitclock check on TX to NOT block when ...</div>~ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd<br /> jshamlet Fri, 11 Dec 2020 18:59:33 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=283 Modified the SDLC core transmit states to have consistent naming. https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=282 <div><strong>Rev 282 - jshamlet</strong> (1 file(s) modified)</div><div>Modified the SDLC core transmit states to have consistent naming.</div>~ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd<br /> jshamlet Fri, 11 Dec 2020 18:37:19 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=282 Added pre-initialization to the dual-port RAM signals. https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=281 <div><strong>Rev 281 - jshamlet</strong> (1 file(s) modified)</div><div>Added pre-initialization to the dual-port RAM signals.</div>~ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd<br /> jshamlet Fri, 11 Dec 2020 15:48:33 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=281 Got rid of silly aliases that connected the dual-port memory ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=280 <div><strong>Rev 280 - jshamlet</strong> (1 file(s) modified)</div><div>Got rid of silly aliases that connected the dual-port memory ...</div>~ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd<br /> jshamlet Fri, 11 Dec 2020 15:09:21 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=280 More comment cleanup https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=279 <div><strong>Rev 279 - jshamlet</strong> (3 file(s) modified)</div><div>More comment cleanup</div>~ /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd<br />~ /open8_urisc/trunk/VHDL/o8_epoch_timer_ii.vhd<br />~ /open8_urisc/trunk/VHDL/o8_register_wide.vhd<br /> jshamlet Thu, 10 Dec 2020 18:08:17 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=279 Flattened the SDLC interface to fewer files and eliminated the ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=278 <div><strong>Rev 278 - jshamlet</strong> (10 file(s) modified)</div><div>Flattened the SDLC interface to fewer files and eliminated the ...</div>~ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd<br />~ /open8_urisc/trunk/VHDL/sdlc_crc16_ccitt.vhd<br />- /open8_urisc/trunk/VHDL/sdlc_serial_arbfsm.vhd<br />- /open8_urisc/trunk/VHDL/sdlc_serial_clk.vhd<br />- /open8_urisc/trunk/VHDL/sdlc_serial_frame.vhd<br />- /open8_urisc/trunk/VHDL/sdlc_serial_pkg.vhd<br />- /open8_urisc/trunk/VHDL/sdlc_serial_rx.vhd<br />- /open8_urisc/trunk/VHDL/sdlc_serial_rxfsm.vhd<br />- /open8_urisc/trunk/VHDL/sdlc_serial_tx.vhd<br />- /open8_urisc/trunk/VHDL/sdlc_serial_txfsm.vhd<br /> jshamlet Thu, 10 Dec 2020 00:10:37 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=278 Fixed documentation errors related to flags. The UPP ALU instruction ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=277 <div><strong>Rev 277 - jshamlet</strong> (2 file(s) modified)</div><div>Fixed documentation errors related to flags. The UPP ALU instruction ...</div>~ /open8_urisc/trunk/Documents/CPU Instruction Set_files/sheet001.htm<br />~ /open8_urisc/trunk/Documents/CPU Instruction Set_files/sheet002.htm<br /> jshamlet Wed, 09 Dec 2020 18:18:20 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=277 More comment fixes https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=276 <div><strong>Rev 276 - jshamlet</strong> (2 file(s) modified)</div><div>More comment fixes</div>~ /open8_urisc/trunk/VHDL/o8_elapsed_usec.vhd<br />~ /open8_urisc/trunk/VHDL/o8_rom_32k.vhd<br /> jshamlet Wed, 04 Nov 2020 21:35:51 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=276 Fixed a minor comment error. https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=275 <div><strong>Rev 275 - jshamlet</strong> (1 file(s) modified)</div><div>Fixed a minor comment error.</div>~ /open8_urisc/trunk/VHDL/o8_trig_delay.vhd<br /> jshamlet Tue, 03 Nov 2020 03:34:19 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=275 Updated comments with more corrections https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=274 <div><strong>Rev 274 - jshamlet</strong> (2 file(s) modified)</div><div>Updated comments with more corrections</div>~ /open8_urisc/trunk/VHDL/o8_async_serial.vhd<br />~ /open8_urisc/trunk/VHDL/o8_trig_delay.vhd<br /> jshamlet Mon, 02 Nov 2020 20:35:23 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=274 Updated comments with corrections https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=273 <div><strong>Rev 273 - jshamlet</strong> (3 file(s) modified)</div><div>Updated comments with corrections</div>~ /open8_urisc/trunk/VHDL/o8_epoch_timer_ii.vhd<br />~ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd<br />~ /open8_urisc/trunk/VHDL/o8_sys_timer.vhd<br /> jshamlet Mon, 02 Nov 2020 18:54:24 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=273 Updated the HTML documentation to reflect the removed generic. https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=272 <div><strong>Rev 272 - jshamlet</strong> (3 file(s) modified)</div><div>Updated the HTML documentation to reflect the removed generic.</div>~ /open8_urisc/trunk/Documents/CPU Instruction Set_files/sheet001.htm<br />~ /open8_urisc/trunk/Documents/CPU Instruction Set_files/sheet002.htm<br />~ /open8_urisc/trunk/Documents/CPU Instruction Set_files/stylesheet.css<br /> jshamlet Fri, 23 Oct 2020 19:31:24 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2F&rev=272
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