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Sat, 13 Jun 2026 14:50:27 +0100FeedCreator 1.7.2Fixed issue where Write_Fault wasn't defaulting to '0' when Write_Protect ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=259
<div><strong>Rev 259 - jshamlet</strong> (4 file(s) modified)</div><div>Fixed issue where Write_Fault wasn't defaulting to '0' when Write_Protect ...</div>~ /open8_urisc/trunk/VHDL/o8_elapsed_usec.vhd<br />+ /open8_urisc/trunk/VHDL/o8_interval_meas.vhd<br />~ /open8_urisc/trunk/VHDL/o8_ram_1k.vhd<br />~ /open8_urisc/trunk/VHDL/o8_ram_4k.vhd<br />jshamletThu, 11 Jun 2020 18:49:08 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=259Fixed write bug in o8_ltc2355_2p.vhd, added a newer Open8_cfg.vhd, and ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=258
<div><strong>Rev 258 - jshamlet</strong> (3 file(s) modified)</div><div>Fixed write bug in o8_ltc2355_2p.vhd, added a newer Open8_cfg.vhd, and ...</div>~ /open8_urisc/trunk/VHDL/o8_ltc2355_2p.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_cfg.vhd<br />+ /open8_urisc/trunk/VHDL/sys_tick.vhd<br />jshamletWed, 10 Jun 2020 21:11:13 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=258Fixed misnamed signal in o8_7seg.vhd and added a replacement switch ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=257
<div><strong>Rev 257 - jshamlet</strong> (2 file(s) modified)</div><div>Fixed misnamed signal in o8_7seg.vhd and added a replacement switch ...</div>~ /open8_urisc/trunk/VHDL/o8_7seg.vhd<br />+ /open8_urisc/trunk/VHDL/o8_switch_if.vhd<br />jshamletWed, 10 Jun 2020 20:22:20 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=257Removed unused generic from the status_led.vhd and cleaned up comments ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=256
<div><strong>Rev 256 - jshamlet</strong> (2 file(s) modified)</div><div>Removed unused generic from the status_led.vhd and cleaned up comments ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/status_led.vhd<br />jshamletWed, 10 Jun 2020 19:29:37 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=256Modified code to make ModelSim happy (It didn't like the ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=255
<div><strong>Rev 255 - jshamlet</strong> (1 file(s) modified)</div><div>Modified code to make ModelSim happy (It didn't like the ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />jshamletWed, 10 Jun 2020 15:01:48 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=255Simplified the ISR address logic so that the upper 12 ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=254
<div><strong>Rev 254 - jshamlet</strong> (1 file(s) modified)</div><div>Simplified the ISR address logic so that the upper 12 ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />jshamletWed, 10 Jun 2020 00:21:03 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=254Fixed spelling error in comment
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=253
<div><strong>Rev 253 - jshamlet</strong> (1 file(s) modified)</div><div>Fixed spelling error in comment</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />jshamletTue, 09 Jun 2020 23:58:30 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=253(This time the CPU model was included...)
Added the ability to ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=252
<div><strong>Rev 252 - jshamlet</strong> (1 file(s) modified)</div><div>(This time the CPU model was included...)<br />
Added the ability to ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />jshamletTue, 09 Jun 2020 23:39:06 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=252Added RAM write fault detection, which can be used to ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=251
<div><strong>Rev 251 - jshamlet</strong> (4 file(s) modified)</div><div>Added RAM write fault detection, which can be used to ...</div>~ /open8_urisc/trunk/VHDL/o8_ram_1k.vhd<br />~ /open8_urisc/trunk/VHDL/o8_ram_4k.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br />~ /open8_urisc/trunk/VHDL/status_led.vhd<br />jshamletTue, 09 Jun 2020 23:37:42 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=251Removed monitor RAM from SDLC model, as it is now ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=250
<div><strong>Rev 250 - jshamlet</strong> (2 file(s) modified)</div><div>Removed monitor RAM from SDLC model, as it is now ...</div>~ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd<br />- /open8_urisc/trunk/VHDL/sdlc_monitor.vhd<br />jshamletFri, 05 Jun 2020 15:33:28 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=250Added a 32-bit wide register and split the status_led core ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=249
<div><strong>Rev 249 - jshamlet</strong> (3 file(s) modified)</div><div>Added a 32-bit wide register and split the status_led core ...</div>+ /open8_urisc/trunk/VHDL/o8_register_wide.vhd<br />~ /open8_urisc/trunk/VHDL/o8_status_led.vhd<br />+ /open8_urisc/trunk/VHDL/status_led.vhd<br />jshamletSun, 24 May 2020 23:50:09 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=249Removed Default_Int_Flag generic from CPU, as it is duplicated by ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=248
<div><strong>Rev 248 - jshamlet</strong> (1 file(s) modified)</div><div>Removed Default_Int_Flag generic from CPU, as it is duplicated by ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />jshamletSun, 24 May 2020 16:01:29 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=248Fixed problem where parallel interface was always forcing the data ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=247
<div><strong>Rev 247 - jshamlet</strong> (1 file(s) modified)</div><div>Fixed problem where parallel interface was always forcing the data ...</div>~ /open8_urisc/trunk/VHDL/o8_vector_rx.vhd<br />jshamletSat, 23 May 2020 22:47:06 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=247The system timer module now allows for an optional millisecond ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=246
<div><strong>Rev 246 - jshamlet</strong> (2 file(s) modified)</div><div>The system timer module now allows for an optional millisecond ...</div>~ /open8_urisc/trunk/VHDL/o8_sys_timer.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vector_rx.vhd<br />jshamletSat, 23 May 2020 17:36:40 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=246Modified the CPU's Supervisor_Mode to also protect SMSK and RSP ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=245
<div><strong>Rev 245 - jshamlet</strong> (2 file(s) modified)</div><div>Modified the CPU's Supervisor_Mode to also protect SMSK and RSP ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />+ /open8_urisc/trunk/VHDL/o8_int_mgr.vhd<br />jshamletThu, 21 May 2020 18:31:22 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=245Added two new generics to the CPU model. The first ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=244
<div><strong>Rev 244 - jshamlet</strong> (33 file(s) modified)</div><div>Added two new generics to the CPU model. The first ...</div>~ /open8_urisc/trunk/VHDL/o8_7seg.vhd<br />~ /open8_urisc/trunk/VHDL/o8_alu16.vhd<br />~ /open8_urisc/trunk/VHDL/o8_async_serial.vhd<br />~ /open8_urisc/trunk/VHDL/o8_btn_int.vhd<br />~ /open8_urisc/trunk/VHDL/o8_clk_detect.vhd<br />~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/o8_crc16_ccitt.vhd<br />~ /open8_urisc/trunk/VHDL/o8_datalatch.vhd<br />~ /open8_urisc/trunk/VHDL/o8_elapsed_usec.vhd<br />~ /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd<br />~ /open8_urisc/trunk/VHDL/o8_epoch_timer_ii.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpin.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpio.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpout.vhd<br />~ /open8_urisc/trunk/VHDL/o8_hd44780_4b.vhd<br />~ /open8_urisc/trunk/VHDL/o8_hd44780_8b.vhd<br />~ /open8_urisc/trunk/VHDL/o8_lfsr32.vhd<br />~ /open8_urisc/trunk/VHDL/o8_ltc2355_2p.vhd<br />~ /open8_urisc/trunk/VHDL/o8_max7221.vhd<br />~ /open8_urisc/trunk/VHDL/o8_pwm16.vhd<br />~ /open8_urisc/trunk/VHDL/o8_pwm_adc.vhd<br />~ /open8_urisc/trunk/VHDL/o8_ram_1k.vhd<br />~ /open8_urisc/trunk/VHDL/o8_ram_4k.vhd<br />~ /open8_urisc/trunk/VHDL/o8_register.vhd<br />~ /open8_urisc/trunk/VHDL/o8_rtc.vhd<br />~ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd<br />~ /open8_urisc/trunk/VHDL/o8_status_led.vhd<br />~ /open8_urisc/trunk/VHDL/o8_sys_timer.vhd<br />~ /open8_urisc/trunk/VHDL/o8_sys_timer_ii.vhd<br />+ /open8_urisc/trunk/VHDL/o8_trig_delay.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vdsm8.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vdsm12.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vector_rx.vhd<br />jshamletWed, 20 May 2020 22:10:07 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=244Optimized code to prefer RAM vs register.
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=243
<div><strong>Rev 243 - jshamlet</strong> (2 file(s) modified)</div><div>Optimized code to prefer RAM vs register.</div>~ /open8_urisc/trunk/VHDL/o8_ram_1k.vhd<br />~ /open8_urisc/trunk/VHDL/o8_ram_4k.vhd<br />jshamletWed, 13 May 2020 18:52:34 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=243Added write protect logic to the RAM cores and system ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=242
<div><strong>Rev 242 - jshamlet</strong> (3 file(s) modified)</div><div>Added write protect logic to the RAM cores and system ...</div>~ /open8_urisc/trunk/VHDL/o8_ram_1k.vhd<br />~ /open8_urisc/trunk/VHDL/o8_ram_4k.vhd<br />~ /open8_urisc/trunk/VHDL/o8_sys_timer.vhd<br />jshamletWed, 13 May 2020 18:15:29 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=242Added an Open8 compatible 7-segment display/decoder and uploaded local/private documentation.
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=241
<div><strong>Rev 241 - jshamlet</strong> (12 file(s) modified)</div><div>Added an Open8 compatible 7-segment display/decoder and uploaded local/private documentation.</div>+ /open8_urisc/trunk/Documents/CPU Instruction Set.htm<br />+ /open8_urisc/trunk/Documents/CPU Instruction Set_files<br />+ /open8_urisc/trunk/Documents/CPU Instruction Set_files/filelist.xml<br />+ /open8_urisc/trunk/Documents/CPU Instruction Set_files/sheet001.htm<br />+ /open8_urisc/trunk/Documents/CPU Instruction Set_files/sheet002.htm<br />+ /open8_urisc/trunk/Documents/CPU Instruction Set_files/stylesheet.css<br />+ /open8_urisc/trunk/Documents/CPU Instruction Set_files/tabstrip.htm<br />+ /open8_urisc/trunk/Documents/Open8_as README.txt<br />+ /open8_urisc/trunk/Documents/Open8_link README.txt<br />+ /open8_urisc/trunk/VHDL/o8_7seg.vhd<br />+ /open8_urisc/trunk/VHDL/o8_pwm_adc.vhd<br />+ /open8_urisc/trunk/VHDL/o8_pwm_adc_ram.vhd<br />jshamletFri, 08 May 2020 23:13:57 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=241Simplified the vector tx/rx system to a single line. An ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=240
<div><strong>Rev 240 - jshamlet</strong> (5 file(s) modified)</div><div>Simplified the vector tx/rx system to a single line. An ...</div>~ /open8_urisc/trunk/Sample Projects.zip<br />~ /open8_urisc/trunk/VHDL/o8_sys_timer_ii.vhd<br />+ /open8_urisc/trunk/VHDL/o8_vector_rx.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_cfg.vhd<br />+ /open8_urisc/trunk/VHDL/vector_tx.vhd<br />jshamletWed, 06 May 2020 19:22:39 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=240
