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Sat, 13 Jun 2026 16:29:23 +0100FeedCreator 1.7.2Updated comments with corrections
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=273
<div><strong>Rev 273 - jshamlet</strong> (3 file(s) modified)</div><div>Updated comments with corrections</div>~ /open8_urisc/trunk/VHDL/o8_epoch_timer_ii.vhd<br />~ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd<br />~ /open8_urisc/trunk/VHDL/o8_sys_timer.vhd<br />jshamletMon, 02 Nov 2020 18:54:24 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=273Updated the HTML documentation to reflect the removed generic.
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=272
<div><strong>Rev 272 - jshamlet</strong> (3 file(s) modified)</div><div>Updated the HTML documentation to reflect the removed generic.</div>~ /open8_urisc/trunk/Documents/CPU Instruction Set_files/sheet001.htm<br />~ /open8_urisc/trunk/Documents/CPU Instruction Set_files/sheet002.htm<br />~ /open8_urisc/trunk/Documents/CPU Instruction Set_files/stylesheet.css<br />jshamletFri, 23 Oct 2020 19:31:24 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=272Removed deleted generic define.
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=271
<div><strong>Rev 271 - jshamlet</strong> (1 file(s) modified)</div><div>Removed deleted generic define.</div>~ /open8_urisc/trunk/VHDL/Open8_cfg.vhd<br />jshamletFri, 23 Oct 2020 19:23:40 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=271Moved CPU internal constants to o8_cpu.vhd and replace the generic ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=270
<div><strong>Rev 270 - jshamlet</strong> (3 file(s) modified)</div><div>Moved CPU internal constants to o8_cpu.vhd and replace the generic ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />+ /open8_urisc/trunk/VHDL/o8_version.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br />jshamletFri, 23 Oct 2020 19:21:26 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=270Modified the write data path to use separate enumerated states ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=269
<div><strong>Rev 269 - jshamlet</strong> (2 file(s) modified)</div><div>Modified the write data path to use separate enumerated states ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br />jshamletWed, 21 Oct 2020 05:50:40 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=269Added a 16-input external interrupt manager and dedicated SPI tx-only ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=268
<div><strong>Rev 268 - jshamlet</strong> (5 file(s) modified)</div><div>Added a 16-input external interrupt manager and dedicated SPI tx-only ...</div>+ /open8_urisc/trunk/VHDL/o8_int_mgr16.vhd<br />+ /open8_urisc/trunk/VHDL/o8_spi_16b_tx.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vdsm8.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vdsm12.vhd<br />~ /open8_urisc/trunk/VHDL/vector_tx.vhd<br />jshamletWed, 21 Oct 2020 05:16:24 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=268Corrected the file description to indicate this is an example ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=267
<div><strong>Rev 267 - jshamlet</strong> (1 file(s) modified)</div><div>Corrected the file description to indicate this is an example ...</div>~ /open8_urisc/trunk/VHDL/Open8_cfg.vhd<br />jshamletWed, 21 Oct 2020 05:10:06 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=267Accidentally uploaded incorrect example file for Open8_cfg.vhd
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=266
<div><strong>Rev 266 - jshamlet</strong> (1 file(s) modified)</div><div>Accidentally uploaded incorrect example file for Open8_cfg.vhd</div>~ /open8_urisc/trunk/VHDL/Open8_cfg.vhd<br />jshamletWed, 21 Oct 2020 05:05:44 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=266Fixed a bug where "reg" wasn't being initialized with Poly_Init ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=265
<div><strong>Rev 265 - jshamlet</strong> (1 file(s) modified)</div><div>Fixed a bug where "reg" wasn't being initialized with Poly_Init ...</div>~ /open8_urisc/trunk/VHDL/sdlc_crc16_ccitt.vhd<br />jshamletMon, 20 Jul 2020 20:25:31 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=265Updated comments
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=264
<div><strong>Rev 264 - jshamlet</strong> (1 file(s) modified)</div><div>Updated comments</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />jshamletFri, 10 Jul 2020 23:13:52 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=264Fixed a very old bug in the CPU core where ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=263
<div><strong>Rev 263 - jshamlet</strong> (2 file(s) modified)</div><div>Fixed a very old bug in the CPU core where ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd<br />jshamletFri, 10 Jul 2020 23:00:32 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=263Added comments to LCD controllers - specifically that reading either ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=262
<div><strong>Rev 262 - jshamlet</strong> (2 file(s) modified)</div><div>Added comments to LCD controllers - specifically that reading either ...</div>~ /open8_urisc/trunk/VHDL/o8_hd44780_4b.vhd<br />~ /open8_urisc/trunk/VHDL/o8_hd44780_8b.vhd<br />jshamletWed, 01 Jul 2020 19:28:42 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=262Increased delay timer to 7 bits for button press detection.
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=261
<div><strong>Rev 261 - jshamlet</strong> (1 file(s) modified)</div><div>Increased delay timer to 7 bits for button press detection.</div>~ /open8_urisc/trunk/VHDL/button_db.vhd<br />jshamletWed, 24 Jun 2020 19:32:59 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=261Added missing comments for Sequential_Interrupts generic, as well as comments ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=260
<div><strong>Rev 260 - jshamlet</strong> (1 file(s) modified)</div><div>Added missing comments for Sequential_Interrupts generic, as well as comments ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />jshamletThu, 11 Jun 2020 20:27:20 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=260Fixed issue where Write_Fault wasn't defaulting to '0' when Write_Protect ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=259
<div><strong>Rev 259 - jshamlet</strong> (4 file(s) modified)</div><div>Fixed issue where Write_Fault wasn't defaulting to '0' when Write_Protect ...</div>~ /open8_urisc/trunk/VHDL/o8_elapsed_usec.vhd<br />+ /open8_urisc/trunk/VHDL/o8_interval_meas.vhd<br />~ /open8_urisc/trunk/VHDL/o8_ram_1k.vhd<br />~ /open8_urisc/trunk/VHDL/o8_ram_4k.vhd<br />jshamletThu, 11 Jun 2020 18:49:08 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=259Fixed write bug in o8_ltc2355_2p.vhd, added a newer Open8_cfg.vhd, and ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=258
<div><strong>Rev 258 - jshamlet</strong> (3 file(s) modified)</div><div>Fixed write bug in o8_ltc2355_2p.vhd, added a newer Open8_cfg.vhd, and ...</div>~ /open8_urisc/trunk/VHDL/o8_ltc2355_2p.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_cfg.vhd<br />+ /open8_urisc/trunk/VHDL/sys_tick.vhd<br />jshamletWed, 10 Jun 2020 21:11:13 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=258Fixed misnamed signal in o8_7seg.vhd and added a replacement switch ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=257
<div><strong>Rev 257 - jshamlet</strong> (2 file(s) modified)</div><div>Fixed misnamed signal in o8_7seg.vhd and added a replacement switch ...</div>~ /open8_urisc/trunk/VHDL/o8_7seg.vhd<br />+ /open8_urisc/trunk/VHDL/o8_switch_if.vhd<br />jshamletWed, 10 Jun 2020 20:22:20 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=257Removed unused generic from the status_led.vhd and cleaned up comments ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=256
<div><strong>Rev 256 - jshamlet</strong> (2 file(s) modified)</div><div>Removed unused generic from the status_led.vhd and cleaned up comments ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/status_led.vhd<br />jshamletWed, 10 Jun 2020 19:29:37 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=256Modified code to make ModelSim happy (It didn't like the ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=255
<div><strong>Rev 255 - jshamlet</strong> (1 file(s) modified)</div><div>Modified code to make ModelSim happy (It didn't like the ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />jshamletWed, 10 Jun 2020 15:01:48 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=255Simplified the ISR address logic so that the upper 12 ...
https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=254
<div><strong>Rev 254 - jshamlet</strong> (1 file(s) modified)</div><div>Simplified the ISR address logic so that the upper 12 ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />jshamletWed, 10 Jun 2020 00:21:03 +0100https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2F&rev=254
