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open8_urisc WebSVN RSS feed - open8_urisc https://opencores.org/websvn//websvn/listing?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F& Tue, 17 Mar 2026 09:27:55 +0100 FeedCreator 1.7.2 Added a simple 8-bit, fixed asynchronous serial interface with compile ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=207 <div><strong>Rev 207 - jshamlet</strong> (4 file(s) modified)</div><div>Added a simple 8-bit, fixed asynchronous serial interface with compile ...</div>+ /open8_urisc/trunk/VHDL/async_ser_rx.vhd<br />+ /open8_urisc/trunk/VHDL/async_ser_tx.vhd<br />+ /open8_urisc/trunk/VHDL/fifo_1k_core.vhd<br />+ /open8_urisc/trunk/VHDL/o8_async_serial.vhd<br /> jshamlet Tue, 07 Apr 2020 23:18:45 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=207 Merged interrupt logic with other clocked process. https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=206 <div><strong>Rev 206 - jshamlet</strong> (1 file(s) modified)</div><div>Merged interrupt logic with other clocked process.</div>~ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd<br /> jshamlet Sat, 04 Apr 2020 04:28:27 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=206 More code and comment cleanup for the new SDLC engine https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=205 <div><strong>Rev 205 - jshamlet</strong> (7 file(s) modified)</div><div>More code and comment cleanup for the new SDLC engine</div>~ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd<br />~ /open8_urisc/trunk/VHDL/sdlc_crc16_ccitt.vhd<br />~ /open8_urisc/trunk/VHDL/sdlc_serial_arbfsm.vhd<br />~ /open8_urisc/trunk/VHDL/sdlc_serial_clk.vhd<br />~ /open8_urisc/trunk/VHDL/sdlc_serial_frame.vhd<br />~ /open8_urisc/trunk/VHDL/sdlc_serial_rx.vhd<br />~ /open8_urisc/trunk/VHDL/sdlc_serial_rxfsm.vhd<br /> jshamlet Sat, 04 Apr 2020 04:25:45 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=205 Fixed more incorrect comments https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=204 <div><strong>Rev 204 - jshamlet</strong> (3 file(s) modified)</div><div>Fixed more incorrect comments</div>~ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd<br />~ /open8_urisc/trunk/VHDL/sdlc_serial_rx.vhd<br />~ /open8_urisc/trunk/VHDL/sdlc_serial_txfsm.vhd<br /> jshamlet Sat, 04 Apr 2020 03:44:08 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=204 Removed an extra delay FF from the bitclock rising edge ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=203 <div><strong>Rev 203 - jshamlet</strong> (1 file(s) modified)</div><div>Removed an extra delay FF from the bitclock rising edge ...</div>~ /open8_urisc/trunk/VHDL/sdlc_serial_rx.vhd<br /> jshamlet Fri, 03 Apr 2020 21:39:35 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=203 Fixed receiver bug that caused false flag detection, Split the large ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=202 <div><strong>Rev 202 - jshamlet</strong> (8 file(s) modified)</div><div>Fixed receiver bug that caused false flag detection,<br /> Split the large ...</div>~ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd<br />~ /open8_urisc/trunk/VHDL/sdlc_crc16_ccitt.vhd<br />+ /open8_urisc/trunk/VHDL/sdlc_serial_arbfsm.vhd<br />- /open8_urisc/trunk/VHDL/sdlc_serial_ctrl.vhd<br />+ /open8_urisc/trunk/VHDL/sdlc_serial_frame.vhd<br />~ /open8_urisc/trunk/VHDL/sdlc_serial_rx.vhd<br />+ /open8_urisc/trunk/VHDL/sdlc_serial_rxfsm.vhd<br />+ /open8_urisc/trunk/VHDL/sdlc_serial_txfsm.vhd<br /> jshamlet Fri, 03 Apr 2020 20:58:22 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=202 Fixed comments regarding RX Checksum location https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=201 <div><strong>Rev 201 - jshamlet</strong> (1 file(s) modified)</div><div>Fixed comments regarding RX Checksum location</div>~ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd<br /> jshamlet Wed, 01 Apr 2020 23:38:42 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=201 Renamed dual-port buffer to match other entities. https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=200 <div><strong>Rev 200 - jshamlet</strong> (3 file(s) modified)</div><div>Renamed dual-port buffer to match other entities.</div>~ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd<br />- /open8_urisc/trunk/VHDL/ram_dp512b_core.vhd<br />+ /open8_urisc/trunk/VHDL/sdlc_dp512b_ram.vhd<br /> jshamlet Wed, 01 Apr 2020 23:33:39 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=200 Added monitor ram for debugging and fixed issue with dual-port ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=199 <div><strong>Rev 199 - jshamlet</strong> (4 file(s) modified)</div><div>Added monitor ram for debugging and fixed issue with dual-port ...</div>~ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd<br />+ /open8_urisc/trunk/VHDL/sdlc_monitor.vhd<br />~ /open8_urisc/trunk/VHDL/sdlc_serial_ctrl.vhd<br />~ /open8_urisc/trunk/VHDL/sdlc_serial_pkg.vhd<br /> jshamlet Wed, 01 Apr 2020 23:22:38 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=199 Removed debugging memory https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=198 <div><strong>Rev 198 - jshamlet</strong> (1 file(s) modified)</div><div>Removed debugging memory</div>~ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd<br /> jshamlet Wed, 01 Apr 2020 15:21:42 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=198 Fixed incorrect comments https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=197 <div><strong>Rev 197 - jshamlet</strong> (1 file(s) modified)</div><div>Fixed incorrect comments</div>~ /open8_urisc/trunk/VHDL/o8_clk_detect.vhd<br /> jshamlet Wed, 01 Apr 2020 14:55:39 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=197 Modified the update logic to allow direct writes to offset ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=196 <div><strong>Rev 196 - jshamlet</strong> (2 file(s) modified)</div><div>Modified the update logic to allow direct writes to offset ...</div>~ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd<br />~ /open8_urisc/trunk/VHDL/sdlc_serial_ctrl.vhd<br /> jshamlet Wed, 01 Apr 2020 14:31:31 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=196 Added dual-port RAM core for SDLC interface. https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=195 <div><strong>Rev 195 - jshamlet</strong> (1 file(s) modified)</div><div>Added dual-port RAM core for SDLC interface.</div>+ /open8_urisc/trunk/VHDL/ram_dp512b_core.vhd<br /> jshamlet Tue, 31 Mar 2020 19:44:48 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=195 Cleaned up licensing sections https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=194 <div><strong>Rev 194 - jshamlet</strong> (22 file(s) modified)</div><div>Cleaned up licensing sections</div>~ /open8_urisc/trunk/VHDL/o8_alu16.vhd<br />~ /open8_urisc/trunk/VHDL/o8_clk_detect.vhd<br />~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/o8_crc16_ccitt.vhd<br />~ /open8_urisc/trunk/VHDL/o8_datalatch.vhd<br />~ /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpin.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpio.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpout.vhd<br />~ /open8_urisc/trunk/VHDL/o8_hd44780_4b.vhd<br />~ /open8_urisc/trunk/VHDL/o8_hd44780_8b.vhd<br />~ /open8_urisc/trunk/VHDL/o8_ltc2355_2p.vhd<br />~ /open8_urisc/trunk/VHDL/o8_max7221.vhd<br />~ /open8_urisc/trunk/VHDL/o8_ram_1k.vhd<br />~ /open8_urisc/trunk/VHDL/o8_register.vhd<br />~ /open8_urisc/trunk/VHDL/o8_rom_32k.vhd<br />~ /open8_urisc/trunk/VHDL/o8_rtc.vhd<br />~ /open8_urisc/trunk/VHDL/o8_status_led.vhd<br />~ /open8_urisc/trunk/VHDL/o8_sys_timer.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vdsm8.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vdsm12.vhd<br />~ /open8_urisc/trunk/VHDL/sdlc_serial_pkg.vhd<br /> jshamlet Tue, 31 Mar 2020 19:43:32 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=194 Fixed incorrect comment in o8_alu16.vhd. The value of the write ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=193 <div><strong>Rev 193 - jshamlet</strong> (1 file(s) modified)</div><div>Fixed incorrect comment in o8_alu16.vhd. The value of the write ...</div>~ /open8_urisc/trunk/VHDL/o8_alu16.vhd<br /> jshamlet Tue, 31 Mar 2020 19:09:11 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=193 Added SDLC packet engine https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=192 <div><strong>Rev 192 - jshamlet</strong> (6 file(s) modified)</div><div>Added SDLC packet engine</div>+ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd<br />+ /open8_urisc/trunk/VHDL/sdlc_serial_clk.vhd<br />+ /open8_urisc/trunk/VHDL/sdlc_serial_ctrl.vhd<br />+ /open8_urisc/trunk/VHDL/sdlc_serial_pkg.vhd<br />+ /open8_urisc/trunk/VHDL/sdlc_serial_rx.vhd<br />+ /open8_urisc/trunk/VHDL/sdlc_serial_tx.vhd<br /> jshamlet Tue, 31 Mar 2020 18:56:32 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=192 Cleaned up comments, added back the OPEN8_NULLBUS constant, and added ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=191 <div><strong>Rev 191 - jshamlet</strong> (28 file(s) modified)</div><div>Cleaned up comments, added back the OPEN8_NULLBUS constant, and added ...</div>+ /open8_urisc/trunk/VHDL/button_db.vhd<br />~ /open8_urisc/trunk/VHDL/o8_alu16.vhd<br />~ /open8_urisc/trunk/VHDL/o8_btn_int.vhd<br />~ /open8_urisc/trunk/VHDL/o8_clk_detect.vhd<br />~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/o8_crc16_ccitt.vhd<br />~ /open8_urisc/trunk/VHDL/o8_datalatch.vhd<br />~ /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpin.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpio.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpout.vhd<br />~ /open8_urisc/trunk/VHDL/o8_hd44780_4b.vhd<br />~ /open8_urisc/trunk/VHDL/o8_hd44780_8b.vhd<br />+ /open8_urisc/trunk/VHDL/o8_ltc2355_2p.vhd<br />+ /open8_urisc/trunk/VHDL/o8_max7221.vhd<br />+ /open8_urisc/trunk/VHDL/o8_max7221_fifo.vhd<br />~ /open8_urisc/trunk/VHDL/o8_ram_1k.vhd<br />~ /open8_urisc/trunk/VHDL/o8_register.vhd<br />~ /open8_urisc/trunk/VHDL/o8_rom_32k.vhd<br />~ /open8_urisc/trunk/VHDL/o8_rtc.vhd<br />~ /open8_urisc/trunk/VHDL/o8_status_led.vhd<br />~ /open8_urisc/trunk/VHDL/o8_sys_timer.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vdsm8.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vdsm12.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br />+ /open8_urisc/trunk/VHDL/ram_1k_core.vhd<br />+ /open8_urisc/trunk/VHDL/rom_32k_core.vhd<br />+ /open8_urisc/trunk/VHDL/sdlc_crc16_ccitt.vhd<br /> jshamlet Tue, 31 Mar 2020 18:53:53 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=191 Fixed a bug in CPU where RTI/RTS wasn't idling the ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=190 <div><strong>Rev 190 - jshamlet</strong> (2 file(s) modified)</div><div>Fixed a bug in CPU where RTI/RTS wasn't idling the ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/o8_rtc.vhd<br /> jshamlet Thu, 19 Mar 2020 21:21:41 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=190 Merged changes from private repository, added ceil_log2 function to Open8_pkg, since ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=189 <div><strong>Rev 189 - jshamlet</strong> (11 file(s) modified)</div><div>Merged changes from private repository,<br /> added ceil_log2 function to Open8_pkg, since ...</div>~ /open8_urisc/trunk/VHDL/o8_btn_int.vhd<br />~ /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpin.vhd<br />~ /open8_urisc/trunk/VHDL/o8_hd44780_4b.vhd<br />~ /open8_urisc/trunk/VHDL/o8_hd44780_8b.vhd<br />~ /open8_urisc/trunk/VHDL/o8_rtc.vhd<br />~ /open8_urisc/trunk/VHDL/o8_status_led.vhd<br />~ /open8_urisc/trunk/VHDL/o8_sys_timer.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vdsm8.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vdsm12.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Wed, 18 Mar 2020 20:47:28 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=189 Added a generic to alter the behavior of RTI so ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=188 <div><strong>Rev 188 - jshamlet</strong> (2 file(s) modified)</div><div>Added a generic to alter the behavior of RTI so ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Wed, 18 Mar 2020 18:01:59 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=188

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