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open8_urisc WebSVN RSS feed - open8_urisc https://opencores.org/websvn//websvn/listing?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2Fo8_cpu.vhd& Wed, 22 Apr 2026 14:08:20 +0100 FeedCreator 1.7.2 Modified the timers to reset on new interval write. This ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=210 <div><strong>Rev 210 - jshamlet</strong> (4 file(s) modified)</div><div>Modified the timers to reset on new interval write. This ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/o8_rtc.vhd<br />~ /open8_urisc/trunk/VHDL/o8_sys_timer.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Thu, 09 Apr 2020 14:27:42 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=210 Fixed an issue in the PIT timer that caused an ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=209 <div><strong>Rev 209 - jshamlet</strong> (8 file(s) modified)</div><div>Fixed an issue in the PIT timer that caused an ...</div>~ /open8_urisc/trunk/VHDL/async_ser_rx.vhd<br />~ /open8_urisc/trunk/VHDL/async_ser_tx.vhd<br />~ /open8_urisc/trunk/VHDL/o8_async_serial.vhd<br />~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd<br />+ /open8_urisc/trunk/VHDL/o8_ram_4k.vhd<br />~ /open8_urisc/trunk/VHDL/o8_rtc.vhd<br />+ /open8_urisc/trunk/VHDL/ram_4k_core.vhd<br /> jshamlet Thu, 09 Apr 2020 01:40:42 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=209 Cleaned up licensing sections https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=194 <div><strong>Rev 194 - jshamlet</strong> (22 file(s) modified)</div><div>Cleaned up licensing sections</div>~ /open8_urisc/trunk/VHDL/o8_alu16.vhd<br />~ /open8_urisc/trunk/VHDL/o8_clk_detect.vhd<br />~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/o8_crc16_ccitt.vhd<br />~ /open8_urisc/trunk/VHDL/o8_datalatch.vhd<br />~ /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpin.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpio.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpout.vhd<br />~ /open8_urisc/trunk/VHDL/o8_hd44780_4b.vhd<br />~ /open8_urisc/trunk/VHDL/o8_hd44780_8b.vhd<br />~ /open8_urisc/trunk/VHDL/o8_ltc2355_2p.vhd<br />~ /open8_urisc/trunk/VHDL/o8_max7221.vhd<br />~ /open8_urisc/trunk/VHDL/o8_ram_1k.vhd<br />~ /open8_urisc/trunk/VHDL/o8_register.vhd<br />~ /open8_urisc/trunk/VHDL/o8_rom_32k.vhd<br />~ /open8_urisc/trunk/VHDL/o8_rtc.vhd<br />~ /open8_urisc/trunk/VHDL/o8_status_led.vhd<br />~ /open8_urisc/trunk/VHDL/o8_sys_timer.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vdsm8.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vdsm12.vhd<br />~ /open8_urisc/trunk/VHDL/sdlc_serial_pkg.vhd<br /> jshamlet Tue, 31 Mar 2020 19:43:32 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=194 Cleaned up comments, added back the OPEN8_NULLBUS constant, and added ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=191 <div><strong>Rev 191 - jshamlet</strong> (28 file(s) modified)</div><div>Cleaned up comments, added back the OPEN8_NULLBUS constant, and added ...</div>+ /open8_urisc/trunk/VHDL/button_db.vhd<br />~ /open8_urisc/trunk/VHDL/o8_alu16.vhd<br />~ /open8_urisc/trunk/VHDL/o8_btn_int.vhd<br />~ /open8_urisc/trunk/VHDL/o8_clk_detect.vhd<br />~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/o8_crc16_ccitt.vhd<br />~ /open8_urisc/trunk/VHDL/o8_datalatch.vhd<br />~ /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpin.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpio.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpout.vhd<br />~ /open8_urisc/trunk/VHDL/o8_hd44780_4b.vhd<br />~ /open8_urisc/trunk/VHDL/o8_hd44780_8b.vhd<br />+ /open8_urisc/trunk/VHDL/o8_ltc2355_2p.vhd<br />+ /open8_urisc/trunk/VHDL/o8_max7221.vhd<br />+ /open8_urisc/trunk/VHDL/o8_max7221_fifo.vhd<br />~ /open8_urisc/trunk/VHDL/o8_ram_1k.vhd<br />~ /open8_urisc/trunk/VHDL/o8_register.vhd<br />~ /open8_urisc/trunk/VHDL/o8_rom_32k.vhd<br />~ /open8_urisc/trunk/VHDL/o8_rtc.vhd<br />~ /open8_urisc/trunk/VHDL/o8_status_led.vhd<br />~ /open8_urisc/trunk/VHDL/o8_sys_timer.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vdsm8.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vdsm12.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br />+ /open8_urisc/trunk/VHDL/ram_1k_core.vhd<br />+ /open8_urisc/trunk/VHDL/rom_32k_core.vhd<br />+ /open8_urisc/trunk/VHDL/sdlc_crc16_ccitt.vhd<br /> jshamlet Tue, 31 Mar 2020 18:53:53 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=191 Fixed a bug in CPU where RTI/RTS wasn't idling the ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=190 <div><strong>Rev 190 - jshamlet</strong> (2 file(s) modified)</div><div>Fixed a bug in CPU where RTI/RTS wasn't idling the ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/o8_rtc.vhd<br /> jshamlet Thu, 19 Mar 2020 21:21:41 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=190 Added a generic to alter the behavior of RTI so ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=188 <div><strong>Rev 188 - jshamlet</strong> (2 file(s) modified)</div><div>Added a generic to alter the behavior of RTI so ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Wed, 18 Mar 2020 18:01:59 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=188 Added the CPU_Halt input, only now as an input to ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=187 <div><strong>Rev 187 - jshamlet</strong> (2 file(s) modified)</div><div>Added the CPU_Halt input, only now as an input to ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Mon, 16 Mar 2020 21:46:04 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=187 Merged the interrupt override logic into the case structure, simplifying ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=186 <div><strong>Rev 186 - jshamlet</strong> (2 file(s) modified)</div><div>Merged the interrupt override logic into the case structure, simplifying ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Fri, 13 Mar 2020 21:56:13 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=186 1) Fixed an apparently long-standing bug where the interrupt bit ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=185 <div><strong>Rev 185 - jshamlet</strong> (2 file(s) modified)</div><div>1) Fixed an apparently long-standing bug where the interrupt bit ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Fri, 13 Mar 2020 19:13:36 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=185 Renamed core to o8_cpu to match new naming scheme https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=183 <div><strong>Rev 183 - jshamlet</strong> (3 file(s) modified)</div><div>Renamed core to o8_cpu to match new naming scheme</div>+ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />- /open8_urisc/trunk/VHDL/Open8.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Wed, 11 Mar 2020 18:59:00 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=183 Simplified the address generation logic at the expense of making ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=182 <div><strong>Rev 182 - jshamlet</strong> (2 file(s) modified)</div><div>Simplified the address generation logic at the expense of making ...</div>~ /open8_urisc/trunk/VHDL/Open8.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Wed, 11 Mar 2020 18:56:40 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=182 Altered the RSP instruction to allow the stack pointed to ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=181 <div><strong>Rev 181 - jshamlet</strong> (2 file(s) modified)</div><div>Altered the RSP instruction to allow the stack pointed to ...</div>~ /open8_urisc/trunk/VHDL/Open8.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Tue, 10 Mar 2020 22:36:44 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=181 General code cleanup https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=172 <div><strong>Rev 172 - jshamlet</strong> (7 file(s) modified)</div><div>General code cleanup</div>~ /open8_urisc/trunk/VHDL/o8_alu16.vhd<br />~ /open8_urisc/trunk/VHDL/o8_etc.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpout.vhd<br />~ /open8_urisc/trunk/VHDL/o8_rtc.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vdsm8.vhd<br />~ /open8_urisc/trunk/VHDL/Open8.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Thu, 07 Jan 2016 20:59:18 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=172 Corrected issue with CMP and SBC generating an inverted carry ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=169 <div><strong>Rev 169 - jshamlet</strong> (2 file(s) modified)</div><div>Corrected issue with CMP and SBC generating an inverted carry ...</div>~ /open8_urisc/trunk/VHDL/Open8.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Fri, 13 Nov 2015 20:09:09 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=169 Simplified write data path logic, Converted RTC to packed BCD, Corrected several ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=168 <div><strong>Rev 168 - jshamlet</strong> (2 file(s) modified)</div><div>Simplified write data path logic,<br /> Converted RTC to packed BCD,<br /> Corrected several ...</div>~ /open8_urisc/trunk/VHDL/o8_rtc.vhd<br />~ /open8_urisc/trunk/VHDL/Open8.vhd<br /> jshamlet Thu, 26 Sep 2013 00:00:17 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=168 Updated CPU model; Pipelined ALU control signals to improve fMAX, ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=167 <div><strong>Rev 167 - jshamlet</strong> (8 file(s) modified)</div><div>Updated CPU model; Pipelined ALU control signals to improve fMAX, ...</div>+ /open8_urisc/trunk/VHDL/o8_alu16.vhd<br />+ /open8_urisc/trunk/VHDL/o8_gpin.vhd<br />+ /open8_urisc/trunk/VHDL/o8_gpio.vhd<br />+ /open8_urisc/trunk/VHDL/o8_gpout.vhd<br />+ /open8_urisc/trunk/VHDL/o8_pit.vhd<br />+ /open8_urisc/trunk/VHDL/o8_rtc.vhd<br />+ /open8_urisc/trunk/VHDL/o8_vdsm8.vhd<br />~ /open8_urisc/trunk/VHDL/Open8.vhd<br /> jshamlet Wed, 18 Sep 2013 01:42:00 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=167 Modified the data path to allow the bus to go ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=164 <div><strong>Rev 164 - jshamlet</strong> (1 file(s) modified)</div><div>Modified the data path to allow the bus to go ...</div>~ /open8_urisc/trunk/VHDL/Open8.vhd<br /> jshamlet Thu, 22 Dec 2011 05:57:29 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=164 Added optional generic to specify that the BRK instruction implements ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=162 <div><strong>Rev 162 - jshamlet</strong> (1 file(s) modified)</div><div>Added optional generic to specify that the BRK instruction implements ...</div>~ /open8_urisc/trunk/VHDL/Open8.vhd<br /> jshamlet Thu, 22 Sep 2011 12:57:57 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=162 Optimized for timing, Flattened block structure to single entity. https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=156 <div><strong>Rev 156 - jshamlet</strong> (1 file(s) modified)</div><div>Optimized for timing,<br /> Flattened block structure to single entity.</div>~ /open8_urisc/trunk/VHDL/Open8.vhd<br /> jshamlet Wed, 27 Jul 2011 22:27:44 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=156 Fixed additional interrupt logic bug, Optimized several blocks - including ALU, ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=155 <div><strong>Rev 155 - jshamlet</strong> (1 file(s) modified)</div><div>Fixed additional interrupt logic bug,<br /> Optimized several blocks - including ALU, ...</div>~ /open8_urisc/trunk/VHDL/Open8.vhd<br /> jshamlet Wed, 27 Jul 2011 03:30:16 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=155

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