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open8_urisc WebSVN RSS feed - open8_urisc https://opencores.org/websvn//websvn/listing?repname=open8_urisc&path=& Tue, 28 Nov 2023 15:48:51 +0100 FeedCreator 1.7.2 Switched o8_version.vhd to integer generics to make assignment from higher-level ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=335 <div><strong>Rev 335 - jshamlet</strong> (2 file(s) modified)</div><div>Switched o8_version.vhd to integer generics to make assignment from higher-level ...</div>~ /open8_urisc/trunk/TaskMan.zip<br />~ /open8_urisc/trunk/VHDL/o8_version.vhd<br /> jshamlet Fri, 06 Oct 2023 17:12:49 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=335 Updated version register to match task switcher example and rom ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=334 <div><strong>Rev 334 - jshamlet</strong> (2 file(s) modified)</div><div>Updated version register to match task switcher example and rom ...</div>~ /open8_urisc/trunk/VHDL/o8_version.vhd<br />+ /open8_urisc/trunk/VHDL/rom_8k_core.vhd<br /> jshamlet Thu, 05 Oct 2023 15:23:29 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=334 Fixed missing semicolons in o8_sys_timer_ii.vhd, Added faulting address capture in the ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=333 <div><strong>Rev 333 - jshamlet</strong> (3 file(s) modified)</div><div>Fixed missing semicolons in o8_sys_timer_ii.vhd,<br /> Added faulting address capture in the ...</div>~ /open8_urisc/trunk/VHDL/o8_ram_1k.vhd<br />~ /open8_urisc/trunk/VHDL/o8_ram_4k.vhd<br />~ /open8_urisc/trunk/VHDL/o8_sys_timer_ii.vhd<br /> jshamlet Thu, 05 Oct 2023 03:44:49 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=333 Added initial version of task manager project https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=332 <div><strong>Rev 332 - jshamlet</strong> (1 file(s) modified)</div><div>Added initial version of task manager project</div>+ /open8_urisc/trunk/TaskMan.zip<br /> jshamlet Thu, 05 Oct 2023 00:40:59 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=332 Added custom SPI LCD interface (pending receive side) and watchdog ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=331 <div><strong>Rev 331 - jshamlet</strong> (3 file(s) modified)</div><div>Added custom SPI LCD interface (pending receive side) and watchdog ...</div>+ /open8_urisc/trunk/VHDL/o8_serlcd_tx.vhd<br />~ /open8_urisc/trunk/VHDL/o8_sys_timer_ii.vhd<br />+ /open8_urisc/trunk/VHDL/o8_watchdog.vhd<br /> jshamlet Thu, 05 Oct 2023 00:28:32 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=331 Updated to route RAM write fault signal and force CPU ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=330 <div><strong>Rev 330 - jshamlet</strong> (1 file(s) modified)</div><div>Updated to route RAM write fault signal and force CPU ...</div>~ /open8_urisc/trunk/VHDL/o8_ts_ioctl.vhd<br /> jshamlet Thu, 28 Sep 2023 17:30:52 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=330 Added a core that specifically supports the task switcher software. ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=329 <div><strong>Rev 329 - jshamlet</strong> (1 file(s) modified)</div><div>Added a core that specifically supports the task switcher software. ...</div>+ /open8_urisc/trunk/VHDL/o8_ts_ioctl.vhd<br /> jshamlet Thu, 28 Sep 2023 16:39:56 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=329 Documentation cleanup. Also added operand definitions. https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=328 <div><strong>Rev 328 - jshamlet</strong> (4 file(s) modified)</div><div>Documentation cleanup. Also added operand definitions.</div>~ /open8_urisc/trunk/Documents/CPU Instruction Set.htm<br />~ /open8_urisc/trunk/Documents/CPU Instruction Set_files/sheet001.htm<br />~ /open8_urisc/trunk/Documents/CPU Instruction Set_files/sheet002.htm<br />~ /open8_urisc/trunk/Documents/CPU Instruction Set_files/stylesheet.css<br /> jshamlet Wed, 27 Sep 2023 19:46:08 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=328 More bug fixes: Added write qual line to LTC2355 interface, fixed ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=327 <div><strong>Rev 327 - jshamlet</strong> (3 file(s) modified)</div><div>More bug fixes:<br /> Added write qual line to LTC2355 interface, fixed ...</div>~ /open8_urisc/trunk/VHDL/o8_ltc2355_2p.vhd<br />~ /open8_urisc/trunk/VHDL/o8_mavg_8ch_16b_64d.vhd<br />+ /open8_urisc/trunk/VHDL/romtape.hex<br /> jshamlet Wed, 27 Sep 2023 15:17:24 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=327 Minor comment correction https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=326 <div><strong>Rev 326 - jshamlet</strong> (1 file(s) modified)</div><div>Minor comment correction</div>~ /open8_urisc/trunk/VHDL/o8_scale_conv.vhd<br /> jshamlet Thu, 21 Sep 2023 17:51:01 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=326 Added the rest of the initializers to the signal assignments https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=325 <div><strong>Rev 325 - jshamlet</strong> (1 file(s) modified)</div><div>Added the rest of the initializers to the signal assignments</div>~ /open8_urisc/trunk/VHDL/o8_mavg_8ch_16b_64d.vhd<br /> jshamlet Thu, 21 Sep 2023 16:43:45 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=325 Modified the Open8 version of the multi-channel roll average code ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=324 <div><strong>Rev 324 - jshamlet</strong> (2 file(s) modified)</div><div>Modified the Open8 version of the multi-channel roll average code ...</div>~ /open8_urisc/trunk/VHDL/o8_mavg_8ch_16b_64d.vhd<br />+ /open8_urisc/trunk/VHDL/o8_romtape_8k.vhd<br /> jshamlet Thu, 21 Sep 2023 16:30:14 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=324 Forgot to add files https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=323 <div><strong>Rev 323 - jshamlet</strong> (2 file(s) modified)</div><div>Forgot to add files</div>+ /open8_urisc/trunk/VHDL/o8_mavg_8ch_16b_64d.vhd<br />+ /open8_urisc/trunk/VHDL/threshold_comp.vhd<br /> jshamlet Wed, 20 Sep 2023 18:06:38 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=323 Performance fixes for the LCD interface, Fixed incorrect entity name for ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=322 <div><strong>Rev 322 - jshamlet</strong> (5 file(s) modified)</div><div>Performance fixes for the LCD interface,<br /> Fixed incorrect entity name for ...</div>~ /open8_urisc/trunk/VHDL/hd44780_4b.vhd<br />~ /open8_urisc/trunk/VHDL/hd44780_8b.vhd<br />~ /open8_urisc/trunk/VHDL/o8_hd44780_8b.vhd<br />~ /open8_urisc/trunk/VHDL/o8_hd44780_if.vhd<br />~ /open8_urisc/trunk/VHDL/o8_ltc2355_2p.vhd<br /> jshamlet Wed, 20 Sep 2023 18:05:56 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=322 Fixed issue with parity flag in receiver sticking https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=321 <div><strong>Rev 321 - jshamlet</strong> (1 file(s) modified)</div><div>Fixed issue with parity flag in receiver sticking</div>~ /open8_urisc/trunk/VHDL/async_ser_rx.vhd<br /> jshamlet Fri, 09 Jun 2023 00:55:42 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=321 Inverted flow control signals to match EIA-232 specification https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=320 <div><strong>Rev 320 - jshamlet</strong> (1 file(s) modified)</div><div>Inverted flow control signals to match EIA-232 specification</div>~ /open8_urisc/trunk/VHDL/o8_async_serial.vhd<br /> jshamlet Tue, 06 Jun 2023 22:06:10 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=320 Fixed off-by-one error in channel count https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=319 <div><strong>Rev 319 - jshamlet</strong> (1 file(s) modified)</div><div>Fixed off-by-one error in channel count</div>~ /open8_urisc/trunk/VHDL/adc128s022.vhd<br /> jshamlet Mon, 05 Jun 2023 18:52:49 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=319 Added o8_scale_conv.vhd and intdiv.vhd https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=318 <div><strong>Rev 318 - jshamlet</strong> (2 file(s) modified)</div><div>Added o8_scale_conv.vhd and intdiv.vhd</div>+ /open8_urisc/trunk/VHDL/intdiv.vhd<br />+ /open8_urisc/trunk/VHDL/o8_scale_conv.vhd<br /> jshamlet Thu, 01 Jun 2023 16:45:53 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=318 Altered the reinit signal on teh adc128s022.vhd driver to be ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=317 <div><strong>Rev 317 - jshamlet</strong> (2 file(s) modified)</div><div>Altered the reinit signal on teh adc128s022.vhd driver to be ...</div>~ /open8_urisc/trunk/VHDL/adc128s022.vhd<br />~ /open8_urisc/trunk/VHDL/o8_de0_nano_adc_if.vhd<br /> jshamlet Thu, 18 May 2023 20:09:33 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=317 More code cleanup and comments, Removed INT_VECTOR_n constants, as they are ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=316 <div><strong>Rev 316 - jshamlet</strong> (1 file(s) modified)</div><div>More code cleanup and comments,<br /> Removed INT_VECTOR_n constants, as they are ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br /> jshamlet Thu, 18 May 2023 20:02:35 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2F&rev=316
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