OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Error creating feed file, please check write permissions.
openmsp430 WebSVN RSS feed - openmsp430 https://opencores.org/websvn//websvn/listing?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F& Fri, 29 Mar 2024 05:28:03 +0100 FeedCreator 1.7.2 Add custom printf function to reduce program memory footprint (the ... https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=211 <div><strong>Rev 211 - olivier.girard</strong> (38 file(s) modified)</div><div>Add custom printf function to reduce program memory footprint (the ...</div>~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/coremark.h<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/coremark_v1.0.v<br />- /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/copydata.c<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/core_portme.mak<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/linker.msp430-elf.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/linker.msp430.x<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/mylib<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/mylib/copydata.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/mylib/cprintf.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/mylib/cprintf.h<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/omsp_func.c<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/omsp_func.h<br />- /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/copydata.c<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/linker.msp430-elf.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/makefile<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/mylib<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/mylib/copydata.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/mylib/cprintf.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/mylib/cprintf.h<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/omsp_func.c<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/omsp_func.h<br />- /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/copydata.c<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/linker.msp430-elf.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/makefile<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/mylib<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/mylib/copydata.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/mylib/cprintf.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/mylib/cprintf.h<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/omsp_func.c<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/omsp_func.h<br />- /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/copydata.c<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.msp430-elf.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/makefile<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/mylib<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/mylib/copydata.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/mylib/cprintf.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/mylib/cprintf.h<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/omsp_system.h<br /> olivier.girard Tue, 17 Nov 2015 11:03:44 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=211 Simulation now works seamlessly under Linux, OS-X and Windows (Cygwin) https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=207 <div><strong>Rev 207 - olivier.girard</strong> (4 file(s) modified)</div><div>Simulation now works seamlessly under Linux, OS-X and Windows (Cygwin)</div>~ /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh<br /> olivier.girard Tue, 20 Oct 2015 20:58:27 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=207 Fix DMA interface RTL merge problem (defines got wrong values). ... https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=204 <div><strong>Rev 204 - olivier.girard</strong> (12 file(s) modified)</div><div>Fix DMA interface RTL merge problem (defines got wrong values). ...</div>~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.s43<br />~ /openmsp430/trunk/doc/html/dma_interface.html<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/periph/omsp_timerA.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/omsp_timerA.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/periph/omsp_timerA.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/omsp_timerA.v<br /> olivier.girard Wed, 08 Jul 2015 20:34:10 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=204 Add DMA interface support + LINT cleanup https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=202 <div><strong>Rev 202 - olivier.girard</strong> (254 file(s) modified)</div><div>Add DMA interface support + LINT cleanup</div>+ /openmsp430/trunk/core/bench/verilog/dma_tasks.v<br />~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v<br />+ /openmsp430/trunk/core/rtl/verilog/filelist.f<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_alu.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_and_gate.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_gate.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_mux.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_i2c.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_scan_mux.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_sfr.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_sync_cell.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_sync_reset.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_wakeup_cell.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/parse_results<br />+ /openmsp430/trunk/core/sim/rtl_sim/bin/parse_summaries<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/template_defs.asm<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all_mpy<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_c<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_disassemble<br />+ /openmsp430/trunk/core/sim/rtl_sim/run/simvision.svcf<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/coremark_v1.0.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/dhrystone_4mcu.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhrystone_v2.1.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/sandbox.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_mclk.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_smclk.v<br />- /openmsp430/trunk/core/sim/rtl_sim/src/core.f<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/cpu_startup_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_cpu.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_halt_irq.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk0.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk1.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk2.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk3.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_mem.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_rdwr.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_sync.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_cpu.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_halt_irq.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk0.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk1.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk2.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk3.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_mem.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_rdwr.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_sync.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dma_dbg_arbiter.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dma_dbg_arbiter.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm0_asic.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm0_asic.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm1_asic.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm1_asic.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm2_asic.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm2_asic.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm3_asic.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm3_asic.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm4_asic.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm4_asic.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dma_rdwr_8b.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dma_rdwr_8b.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dma_rdwr_16b.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dma_rdwr_16b.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dma_resp.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dma_resp.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/irq32.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/irq64.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mac.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_macs.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpy.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpys.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/nmi.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sandbox.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sandbox.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/scan.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/submit.f<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_output.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_wkup.v<br />~ /openmsp430/trunk/doc/html/core.html<br />+ /openmsp430/trunk/doc/html/dma_interface.html<br />~ /openmsp430/trunk/doc/html/images/core_integration.odg<br />~ /openmsp430/trunk/doc/html/images/core_integration.png<br />~ /openmsp430/trunk/doc/html/images/cpu_structure.odg<br />~ /openmsp430/trunk/doc/html/images/cpu_structure.png<br />+ /openmsp430/trunk/doc/html/images/dma_bootloader.png<br />+ /openmsp430/trunk/doc/html/images/dma_clock_domains.png<br />+ /openmsp430/trunk/doc/html/images/dma_interface.odg<br />+ /openmsp430/trunk/doc/html/images/dma_interface_complex_sys.png<br />+ /openmsp430/trunk/doc/html/images/dma_interface_simple_sys.png<br />+ /openmsp430/trunk/doc/html/images/dma_waveforms.odg<br />+ /openmsp430/trunk/doc/html/images/dma_waveform_bootloader.png<br />+ /openmsp430/trunk/doc/html/images/dma_waveform_error_resp.png<br />+ /openmsp430/trunk/doc/html/images/dma_waveform_multiple.png<br />+ /openmsp430/trunk/doc/html/images/dma_waveform_priority.png<br />+ /openmsp430/trunk/doc/html/images/dma_waveform_simple.png<br />+ /openmsp430/trunk/doc/html/images/dma_waveform_wait_states.png<br />+ /openmsp430/trunk/doc/html/images/wave_dma.odg<br />+ /openmsp430/trunk/doc/html/images/wave_dma.png<br />~ /openmsp430/trunk/doc/html/integration.html<br />~ /openmsp430/trunk/doc/html/overview.html<br />~ /openmsp430/trunk/doc/html/peripherals.html<br />~ /openmsp430/trunk/doc/html/serial_debug_interface.html<br />~ /openmsp430/trunk/doc/openMSP430.odt<br />~ /openmsp430/trunk/doc/openMSP430.pdf<br />+ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/filelist.f<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_alu.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_and_gate.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_gate.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_mux.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_i2c.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_uart.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_mem_backbone.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_register_file.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_scan_mux.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sfr.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sync_cell.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sync_reset.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_wakeup_cell.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_watchdog.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/linker.x<br />+ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/filelist.f<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_alu.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_and_gate.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_gate.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_module.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_mux.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_i2c.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_uart.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_frontend.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_mem_backbone.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_register_file.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_scan_mux.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sfr.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sync_cell.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sync_reset.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_wakeup_cell.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_watchdog.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_undefines.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/OpenMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/software/memledtest/link.ld<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/omsp_system_0.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/omsp_system_1.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/omsp_uart.v<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/filelist.f<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_alu.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_and_gate.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_clock_gate.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_clock_module.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_clock_mux.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_dbg_i2c.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_dbg_uart.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_frontend.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_mem_backbone.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_register_file.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_scan_mux.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_sfr.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_sync_cell.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_sync_reset.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_wakeup_cell.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_watchdog.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430_undefines.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/sim/rtl_sim/src/submit.f<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/software/leds/linker.x<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/omsp_uart.v<br />+ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/filelist.f<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_alu.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_and_gate.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_gate.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_module.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_mux.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_i2c.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_uart.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_frontend.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_mem_backbone.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_register_file.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_scan_mux.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sfr.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sync_cell.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sync_reset.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_wakeup_cell.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_watchdog.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openMSP430_fpga.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/hw_uart/linker.x<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/leds/linker.x<br /> olivier.girard Wed, 01 Jul 2015 21:13:32 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=202 Major verificaiton and benchmark update to support both MSPGCC ... https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=200 <div><strong>Rev 200 - olivier.girard</strong> (99 file(s) modified)</div><div>Major verificaiton and benchmark update to support both MSPGCC ...</div>~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/template_defs.asm<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all_mpy<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_c<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_disassemble<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/coremark_v1.0.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/copydata.c<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/core_portme.mak<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/linker.msp430-elf.x<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/linker.msp430.x<br />- /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/linker.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/omsp_func.h<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/copydata.c<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/dhry.h<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/dhrystone_4mcu.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/linker.msp430-elf.x<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/linker.msp430.x<br />- /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/linker.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/makefile<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/omsp_func.h<br />- /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/z8obj<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/copydata.c<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhry.h<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhrystone_v2.1.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhry_1.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/linker.msp430-elf.x<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/linker.msp430.x<br />- /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/linker.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/makefile<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/omsp_func.h<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/copydata.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.msp430-elf.x<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.msp430.x<br />- /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/makefile<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/omsp_system.h<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_mem.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_mem.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_sync.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_mem.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_mem.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/nmi.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rra.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rrc.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_swpb.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_sxt.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_16b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add_rom-rd.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr-b.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.s43<br />- /openmsp430/trunk/core/synthesis/synopsys/results<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_dmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3adsp_pmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_dmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3a_pmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_dmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3e_pmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_dmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan3_pmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_dmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/spartan6_pmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/tmp<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_dmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex4_pmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_dmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex5_pmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_dmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/virtex6_pmem_xdb<br />- /openmsp430/trunk/core/synthesis/xilinx/src/coregen/_xmsgs<br />+ /openmsp430/trunk/doc/toolchain_benchmark.txt<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v<br />- /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/xlnx_auto_0_xdb<br />- /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430.v<br />- /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/coregen/tmp<br />- /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/coregen/xlnx_auto_0_xdb<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v<br /> olivier.girard Wed, 21 Jan 2015 22:01:31 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=200 Number of supported IRQs is now configurable to 14 (default), ... https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=192 <div><strong>Rev 192 - olivier.girard</strong> (18 file(s) modified)</div><div>Number of supported IRQs is now configurable to 14 (default), ...</div>~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_alu.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/template.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_sync.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/irq32.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/irq32.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/irq64.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/irq64.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/nmi.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.v<br /> olivier.girard Tue, 17 Dec 2013 20:15:28 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=192 Fixed Hardware Multiplier byte operations bug: http://opencores.org/bug,assign,2247 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=186 <div><strong>Rev 186 - olivier.girard</strong> (7 file(s) modified)</div><div>Fixed Hardware Multiplier byte operations bug: <a href="http://opencores.org/bug,assign,2247" target="_blank">http://opencores.org/bug,assign,2247</a></div>~ /openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_multiplier.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v<br /> olivier.girard Mon, 08 Apr 2013 20:00:10 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=186 Add new ASIC_CLOCKING configuration option to allow ASIC implementations with ... https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=180 <div><strong>Rev 180 - olivier.girard</strong> (29 file(s) modified)</div><div>Add new ASIC_CLOCKING configuration option to allow ASIC implementations with ...</div>~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_sfr.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_mclk.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_smclk.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/cpu_startup_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_output.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_wkup.v<br /> olivier.girard Mon, 25 Feb 2013 21:23:18 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=180 Update all linker scripts with a simplified version. Thanks to Mihai ... https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=178 <div><strong>Rev 178 - olivier.girard</strong> (11 file(s) modified)</div><div>Update all linker scripts with a simplified version.<br /> Thanks to Mihai ...</div>~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/linker.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/linker.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/linker.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/ldscript_example.x<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/linker.x<br />~ /openmsp430/trunk/fpga/altera_de1_board/software/memledtest/link.ld<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/software/leds/linker.x<br /> olivier.girard Sat, 16 Feb 2013 21:39:23 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=178 Update hardware breakpoint unit with the followings: - fixed hardware breakpoint ... https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=175 <div><strong>Rev 175 - olivier.girard</strong> (14 file(s) modified)</div><div>Update hardware breakpoint unit with the followings:<br /> - fixed hardware breakpoint ...</div>~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk0.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk1.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk2.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk3.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_rdwr.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk0.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk1.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk2.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk3.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_rdwr.v<br />~ /openmsp430/trunk/core/synthesis/synopsys/read.tcl<br /> olivier.girard Wed, 30 Jan 2013 21:21:42 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=175 The serial debug interface now supports the I2C protocol (in ... https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=154 <div><strong>Rev 154 - olivier.girard</strong> (82 file(s) modified)</div><div>The serial debug interface now supports the I2C protocol (in ...</div>+ /openmsp430/trunk/core/bench/verilog/dbg_i2c_tasks.v<br />~ /openmsp430/trunk/core/bench/verilog/dbg_uart_tasks.v<br />+ /openmsp430/trunk/core/bench/verilog/io_cell.v<br />~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v<br />+ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_i2c.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_sfr.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/template_defs.asm<br />~ /openmsp430/trunk/core/sim/rtl_sim/run<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/core.f<br />- /openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.s43<br />- /openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.v<br />- /openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.s43<br />- /openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.v<br />- /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.s43<br />- /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.v<br />- /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.s43<br />- /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.v<br />- /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.s43<br />- /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.v<br />- /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.s43<br />- /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_cpu.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_cpu.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_halt_irq.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_halt_irq.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk0.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk0.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk1.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk1.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk2.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk2.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk3.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk3.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_mem.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_mem.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff_asic.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff_asic.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_rdwr.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_rdwr.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_sync.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_sync.v<br />- /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.s43<br />- /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v<br />- /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.s43<br />- /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.v<br />- /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff_asic.s43<br />- /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff_asic.v<br />- /openmsp430/trunk/core/sim/rtl_sim/src/dbg_rdwr.s43<br />- /openmsp430/trunk/core/sim/rtl_sim/src/dbg_rdwr.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_cpu.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_cpu.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_halt_irq.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_halt_irq.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk0.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk0.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk1.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk1.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk2.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk2.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk3.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk3.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_mem.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_mem.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff_asic.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff_asic.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_rdwr.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_rdwr.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sfr.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sfr.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/submit.f<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/submit.prj<br /> olivier.girard Mon, 15 Oct 2012 20:44:20 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=154 Add possibility to configure custom Program, Data and Peripheral memory ... https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=151 <div><strong>Rev 151 - olivier.girard</strong> (22 file(s) modified)</div><div>Add possibility to configure custom Program, Data and Peripheral memory ...</div>~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c<br />+ /openmsp430/trunk/core/sim/rtl_sim/bin/omsp_config.sh<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_16b.s43<br />~ /openmsp430/trunk/doc/openMSP430.odt<br />~ /openmsp430/trunk/doc/openMSP430.pdf<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_mem_backbone.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/msp430sim<br />+ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/omsp_config.sh<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_mem_backbone.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/msp430sim<br />+ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/omsp_config.sh<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_mem_backbone.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/msp430sim<br />+ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/omsp_config.sh<br /> olivier.girard Sun, 22 Jul 2012 22:24:11 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=151 Update simulation regression result parser. Fixed failing SFR test (due to ... https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=149 <div><strong>Rev 149 - olivier.girard</strong> (7 file(s) modified)</div><div>Update simulation regression result parser.<br /> Fixed failing SFR test (due to ...</div>~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/bin/parse_results<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sfr.s43<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg.v<br /> olivier.girard Thu, 19 Jul 2012 20:21:12 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=149 Add Dhrystone and CoreMark benchmarks to the simulation environment. https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=145 <div><strong>Rev 145 - olivier.girard</strong> (80 file(s) modified)</div><div>Add Dhrystone and CoreMark benchmarks to the simulation environment.</div>~ /openmsp430/trunk/core/bench/verilog/registers.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/coremark.h<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/coremark.md5<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/coremark_v1.0.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/core_list_join.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/core_main.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/core_matrix.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/core_state.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/core_util.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/docs<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/docs/Coremark-requirements.doc<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/docs/LICENSE.DOC<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/docs/r01an0757eu_rx.pdf<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/LICENSE.txt<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/Makefile<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/core_portme.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/core_portme.h<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/core_portme.mak<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/linker.x<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/omsp_func.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/msp430/omsp_func.h<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/readme.txt<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/release_notes.txt<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/dhry.h<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/dhry21a.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/dhry21b.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/dhrystone_4mcu.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/linker.x<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/makefile<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/omsp_func.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/omsp_func.h<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/dhry.h<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/dhry21a.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/dhry21b.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/Dhrystone.pnproj<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/dhyrstone.pro<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/estubs.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/Makefile<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/ReadMe.txt<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/timers_b.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/original_files/z8obj<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhry.h<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhrystone_v2.1.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhry_1.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhry_2.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/doc<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/doc/reu05b0134_rxap.pdf<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/linker.x<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/makefile<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/omsp_func.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/omsp_func.h<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/bymanuf<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/byperf<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/cc_dry2<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/cc_dry2reg<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/clarify.doc<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/dhry-2.1.p<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/dhry.h<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/dhry.p<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/dhry_1.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/dhry_2.c<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/dhry_c.dif<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/doit<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/Makefile<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/pure2_1.dif<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/RATIONALE<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/README<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/README.RER<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/results<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/original_files/submit.frm<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/sandbox.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/ldscript_example.x<br /> olivier.girard Wed, 30 May 2012 21:03:05 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=145 Beautify the linker script examples. https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=142 <div><strong>Rev 142 - olivier.girard</strong> (2 file(s) modified)</div><div>Beautify the linker script examples.</div>~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/ldscript_example.x<br /> olivier.girard Wed, 09 May 2012 20:19:02 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=142 Update verification environment to support MSPGCC Uniarch (based on GCC ... https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=141 <div><strong>Rev 141 - olivier.girard</strong> (68 file(s) modified)</div><div>Update verification environment to support MSPGCC Uniarch (based on GCC ...</div>~ /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c<br />+ /openmsp430/trunk/core/sim/rtl_sim/bin/template_defs.asm<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/main.c<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/makefile<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/omsp_system.h<br />- /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/periph.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_mclk.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_smclk.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/cpu_startup_asic.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_cpu.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_halt_irq.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk0.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk1.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk2.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_hwbrk3.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff_asic.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_rdwr.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_sync.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_irq.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/gpio_rdwr.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mac.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_macs.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpy.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpys.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/nmi.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sandbox.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sfr.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call_rom-rd.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_push_rom-rd.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rra.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_rrc.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_swpb.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_sxt.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_output.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_8b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/template_periph_16b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add_rom-rd.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr-b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_wkup.s43<br /> olivier.girard Sat, 05 May 2012 21:22:06 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=141 Update simulation scripts to support Cygwin out of the box ... https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=138 <div><strong>Rev 138 - olivier.girard</strong> (13 file(s) modified)</div><div>Update simulation scripts to support Cygwin out of the box ...</div>~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_c<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/bin/rtlsim.sh<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/sim/rtl_sim/run/run<br />~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/rtlsim.sh<br />~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/run/run<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/rtlsim.sh<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/run/run<br /> olivier.girard Mon, 23 Apr 2012 11:10:00 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=138 Add full ASIC support (low-power modes, DFT, ...). Improved serial debug ... https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=134 <div><strong>Rev 134 - olivier.girard</strong> (116 file(s) modified)</div><div>Add full ASIC support (low-power modes, DFT, ...).<br /> Improved serial debug ...</div>~ /openmsp430/trunk/core/bench/verilog/dbg_uart_tasks.v<br />~ /openmsp430/trunk/core/bench/verilog/msp_debug.v<br />~ /openmsp430/trunk/core/bench/verilog/registers.v<br />~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_alu.v<br />+ /openmsp430/trunk/core/rtl/verilog/omsp_and_gate.v<br />+ /openmsp430/trunk/core/rtl/verilog/omsp_clock_gate.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v<br />+ /openmsp430/trunk/core/rtl/verilog/omsp_clock_mux.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v<br />+ /openmsp430/trunk/core/rtl/verilog/omsp_scan_mux.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_sfr.v<br />+ /openmsp430/trunk/core/rtl/verilog/omsp_sync_reset.v<br />+ /openmsp430/trunk/core/rtl/verilog/omsp_wakeup_cell.v<br />~ /openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v<br />~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_gpio.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/omsp_timerA.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v<br />~ /openmsp430/trunk/core/rtl/verilog/periph/template_periph_16b.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/cov_exclude.dat<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/cov_exclude_bits.dat<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/cov_iccr_merge.cf<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/cov_ncverilog.ccf<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh<br />- /openmsp430/trunk/core/sim/rtl_sim/bin/template.def<br />+ /openmsp430/trunk/core/sim/rtl_sim/bin/template.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/load_waveform.sav<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all_mpy<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_c<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_coverage_analysis<br />- /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.def<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/linker.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/main.c<br />~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/makefile<br />+ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/periph.x<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_mclk.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_mclk.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_smclk.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_smclk.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/core.f<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/cpu_startup_asic.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/cpu_startup_asic.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff_asic.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_onoff_asic.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_rdwr.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_rdwr.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_sync.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_sync.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/nmi.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/nmi.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/scan.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/scan.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sfr.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/sfr.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/submit.f<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/submit.prj<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_output.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add-b.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_add.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr-b.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr-b.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_autoincr.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov-b.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/two-op_mov.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.v<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_wkup.s43<br />+ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_wkup.v<br />~ /openmsp430/trunk/core/synthesis/altera/design_files.v<br />~ /openmsp430/trunk/core/synthesis/synopsys/constraints.tcl<br />~ /openmsp430/trunk/core/synthesis/synopsys/read.tcl<br />+ /openmsp430/trunk/core/synthesis/synopsys/run_tmax<br />~ /openmsp430/trunk/core/synthesis/synopsys/synthesis.tcl<br />+ /openmsp430/trunk/core/synthesis/synopsys/tmax.tcl<br />~ /openmsp430/trunk/core/synthesis/xilinx/openMSP430_fpga.prj<br /> olivier.girard Thu, 22 Mar 2012 20:31:06 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=134 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=128 <div><strong>Rev 128 - olivier.girard</strong> (8 file(s) modified)</div><div>Fixed CALL x(SR) bug (see Bugtracker <a href="http://opencores.org/bug,view,2111" target="_blank">http://opencores.org/bug,view,2111</a> )</div>~ /openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/template.def<br />~ /openmsp430/trunk/core/sim/rtl_sim/run<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.s43<br />~ /openmsp430/trunk/core/sim/rtl_sim/src/sing-op_call.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_execution_unit.v<br /> olivier.girard Fri, 16 Dec 2011 21:05:46 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=128 Add coverage report generation (NCVERILOG only) Add support for the ISIM ... https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=122 <div><strong>Rev 122 - olivier.girard</strong> (11 file(s) modified)</div><div>Add coverage report generation (NCVERILOG only)<br /> Add support for the ISIM ...</div>+ /openmsp430/trunk/core/sim/rtl_sim/bin/cov_exclude.dat<br />+ /openmsp430/trunk/core/sim/rtl_sim/bin/cov_exclude_bits.dat<br />+ /openmsp430/trunk/core/sim/rtl_sim/bin/cov_iccr_merge.cf<br />+ /openmsp430/trunk/core/sim/rtl_sim/bin/cov_ncverilog.ccf<br />+ /openmsp430/trunk/core/sim/rtl_sim/bin/cov_ncverilog.tcl<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c<br />~ /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run<br />~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all<br />+ /openmsp430/trunk/core/sim/rtl_sim/run/run_coverage_analysis<br /> olivier.girard Wed, 05 Oct 2011 20:29:45 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2F&rev=122
© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.